# IEEE Transactions on Circuits and Systems II: Express Briefs

## Filter Results

Displaying Results 1 - 25 of 28

Publication Year: 2008, Page(s):C1 - C4
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• ### IEEE Transactions on Circuits and Systems—II: Express Briefs publication information

Publication Year: 2008, Page(s): C2
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• ### Design Considerations for Cascade $Delta Sigma$ ADC's

Publication Year: 2008, Page(s):389 - 393
Cited by:  Papers (9)
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This brief discusses the design tradeoffs for cascaded delta-sigma (DeltaSigma) analog-to-digital converters. Increasing the order of the first loop allows a tradeoff between aggressive noise shaping and moderate operational transconductance amplifier (OTA) specifications. A comparison between fourth-order topologies indicates that for a cascade 3-1 topology, 55-dB OTA gain is sufficient for 96-dB... View full abstract»

• ### Current-Mode High-Accuracy High-Precision CMOS Amplifiers

Publication Year: 2008, Page(s):394 - 398
Cited by:  Papers (17)
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In low-voltage, deep sub- mum analog CMOS circuits, the accuracy and precision can be limited by the finite gain as well as by the input offset and 1/f noise voltages of opamps. Here, we show how to design high-accuracy high-precision CMOS amplifiers by properly applying dynamic element matching to a second-generation current conveyor (CCII); if all of the critical, nominally identical tran... View full abstract»

• ### A Wide-Band CMOS LC VCO With Linearized Coarse Tuning Characteristics

Publication Year: 2008, Page(s):399 - 403
Cited by:  Papers (46)  |  Patents (2)
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A pseudo-exponential capacitor bank structure is proposed to implement a wide-band CMOS LC voltage-controlled oscillator (VCO) with linearized coarse tuning characteristics. An octave bandwidth VCO employing the proposed 6-bit pseudo-exponential capacitor bank structure has been realized in 0.18-mum CMOS. Compared to a conventional VCO employing a binary weighted capacitor bank, the proposed VCO h... View full abstract»

• ### A 50.8–53-GHz Clock Generator Using a Harmonic-Locked PD in 0.13- $mu$m CMOS

Publication Year: 2008, Page(s):404 - 408
Cited by:  Papers (4)
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A 50.8-53-GHz clock generator with a quadruplicate-harmonic-locked phase detector (PD) is presented to achieve a low spur and a low reference frequency. The proposed quadruplicate-harmonic-locked PD, a low-voltage Colpitts voltage-controlled oscillator, and a wide-range divide-by-2 divider are also presented. This clock generator has been fabricated in a 0.13-mum process. The measured reference sp... View full abstract»

• ### A 1-V CMOS Pseudo-Differential Amplifier With Multiple Common-Mode Stabilization and Frequency Compensation Loops

Publication Year: 2008, Page(s):409 - 413
Cited by:  Papers (7)
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This paper presents an operational amplifier for a 1-V supply voltage. It comprises three gain stages with ac-boosting and buffered Miller feedback compensation circuits. The implementation uses a standard 0.35-mum CMOS process ( V and V). To accommodate maximum voltage headroom between power rails, a pseudo-differential structure is adopted in this amplifier. The large common-mode gain associated... View full abstract»

• ### A Magnetic Feedback Method for Low-Voltage CMOS LNA Reverse-Isolation Enhancement

Publication Year: 2008, Page(s):414 - 418
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A magnetic feedback method for enhancing the reverse isolation of low-voltage (1.2-V), single-transistor CMOS low-noise amplifiers (LNAs) is presented. The method neutralizes the gate-drain overlap capacitance of the amplifying transistor, allowing for adequate reverse isolation without gain reduction. The method does not require a differential LNA topology and input matching is facilitated since ... View full abstract»

• ### Physical Modeling of MEMS Variable Inductor

Publication Year: 2008, Page(s):419 - 422
Cited by:  Papers (4)  |  Patents (1)
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In this study, we propose a new equivalent circuit model of variable inductors. We have proposed variable inductors with metal plate moving with a microelectromechanical system (MEMS) actuator. The proposed model consists of a conventional single-pi model, networks for silicon substrate and metal plate flowing eddy current, and coupling coefficients between these networks. The model is verified by... View full abstract»

• ### Known-Plaintext Attack to Two Cryptosystems Based on the BB Equation

Publication Year: 2008, Page(s):423 - 426
Cited by:  Papers (6)
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Recently, Rama Murthy and Swamy proposed a symmetric cryptosystem based on the Brahmagupta-Bhaskara (BB) equation. The BB equation is the quadratic Diophantine equation nx 2 + k = y 2, where k is an integer and n is a positive integer such that radic(n) is irrational. For the particular case k=1, the equation is called the Pell... View full abstract»

• ### Strength-Reduced Parallel Chien Search Architecture for Strong BCH Codes

Publication Year: 2008, Page(s):427 - 431
Cited by:  Papers (19)
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The Chien search process is the most complex block in the decoding of Bose-Chaudhuri-Hochquenghem (BCH) codes. Since the BCH codes conduct the bit-by-bit error correction, they often need a parallel implementation for high throughput applications. The parallel implementation obviously needs much increased hardware. In this paper, we propose a strength reduced architecture for the parallel Chien se... View full abstract»

• ### A 3$,times,$5-Gb/s Multilane Low-Power 0.18-$mu{hbox {m}}$ CMOS Pseudorandom Bit Sequence Generator

Publication Year: 2008, Page(s):432 - 436
Cited by:  Papers (4)
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A low-power, three-lane, pseudorandom bit sequence (PRBS) generator has been fabricated in a 0.18-mum CMOS process to test a multilane multi-Gb/s transmitter that cancels far-end crosstalk. Although the proposed PRBS generator was designed to produce three uncorrelated 12-Gb/s PRBS sequences, measurement results included in this paper have been obtained at only 5 Gb/s due to test setup limitations... View full abstract»

• ### CMOS Differential Logic Family With Conditional Operation for Low-Power Application

Publication Year: 2008, Page(s):437 - 441
Cited by:  Papers (3)
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In this paper, a set of CMOS differential logic circuits are introduced for use in low-power application. They perform a conditional operation for statistical power reduction during logic operation. The self-precharged version of the logic family provides additional power saving by allowing the use of a small-swing clock. Synchronous counters and bidirectional shift registers were designed in a 0.... View full abstract»

• ### Variable Digital Filter With Group Delay Flatness Specification or Phase Constraints

Publication Year: 2008, Page(s):442 - 446
Cited by:  Papers (9)
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In this paper, we consider the design of finite-impulse response variable digital filters (VDFs) with variable cutoff frequency or variable fractional delay. We propose the design of VDFs with minimum integral squared error and constraints on the maximum error deviation in conjunction with flatness group delay specification or phase constraints. These specifications allow the VDFs to have approxim... View full abstract»

• ### Design of Parallel Tomlinson–Harashima Precoders

Publication Year: 2008, Page(s):447 - 451
Cited by:  Papers (3)
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Like decision feedback equalizers (DFEs), Tomlinson-Harashima precoders (TH precoders) contain nonlinear feedback loops, which limit their use for high-speed applications. Unlike in DFEs, where the output levels of the nonlinear devices are finite, in TH precoders the output levels of the modulo devices are either infinite or finite but very large. Thus, it is difficult to apply look-ahead and pre... View full abstract»

• ### A Fractionally Delaying Complex Hilbert Transform Filter

Publication Year: 2008, Page(s):452 - 456
Cited by:  Papers (4)
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In this paper, we present a novel complex discrete-time filter. This is a fractionally delaying (FD) Hilbert transform filter (HTF) further called the FD HTF. The filter is based on a pair of rotated variable fractional delay (VFD) filters. It is capable of performing the Hilbertian as well as VFD filtering of the incoming discrete-time signal at the same time. Thus, one can substitute a cascade o... View full abstract»

• ### Performance of an SIMO FM-DCSK Communication System

Publication Year: 2008, Page(s):457 - 461
Cited by:  Papers (42)
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A single-input multiple-output (SIMO) architecture of the frequency-modulated (FM) differential code-shift keying (DCSK) modulation technique is proposed. The new scheme employs orthogonal Walsh functions at the transmitter, with parallel substreams transmitted with a single antenna to help achieve a significant increase of the data rate. Multiple antennas are used at the receiver end to form an S... View full abstract»

• ### A Note on PIN Polynomials and PRIN Rational Functions

Publication Year: 2008, Page(s):462 - 463
Cited by:  Papers (20)
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This brief presents a necessary and sufficient condition for testing positive, real, imaginary, and negative rational functions. A related term, the positive, imaginary, and negative polynomial, is defined and two necessary and sufficient conditions for testing it are given. View full abstract»

• ### Improvement of State Feedback Controller Design for Networked Control Systems

Publication Year: 2008, Page(s):464 - 468
Cited by:  Papers (55)
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A new method is proposed to improve the state feedback controller design for networked control systems (NCSs) taking both network-induced time delay and packet dropout into account in this paper. An appropriate Lyapunov functional is introduced to establish the improved sufficient stabilizability conditions for NCSs with memoryless state feedback controller by considering an additional useful term... View full abstract»

• ### Networked Predictive Control Systems Based on the Hammerstein Model

Publication Year: 2008, Page(s):469 - 473
Cited by:  Papers (26)
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In this paper, a novel predictive control-based approach is proposed for a networked control system with random delays containing an input nonlinear process based on a Hammerstein model. The method uses a time-delay two-step generalized predictive control scheme, which consists of two parts: one is to deal with the input nonlinearity of the Hammerstein model and the other is to compensate for the ... View full abstract»

• ### All-MOS ASK Demodulator for Low-Frequency Applications

Publication Year: 2008, Page(s):474 - 478
Cited by:  Papers (17)  |  Patents (1)
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A miniature amplitude-shift-keying (ASK) demodulator without any passive elements, i.e., R or C, for low-frequency applications is presented in the paper. The noise margin of the envelope detector in the proposed ASK demodulator is enlarged such that any Schmitt trigger or current limiting resistor is no longer needed. It results in the number of transistors required for the ASK demo... View full abstract»

• ### A Mixed-Signal Vector Modulator for Eigenbeamforming Receivers

Publication Year: 2008, Page(s):479 - 483
Cited by:  Papers (3)
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Analog vector modulators used in eigenbeamforming receivers usually include radio-frequency (RF) variable-gain amplifiers (VGAs) to modulate both the magnitude and the phase of receiving signals. The strenuous linearity requirement of RF VGAs makes it unsuitable to be realized in CMOS. This paper applies the mathematical concept of overcomplete expansion and coarse quantization to replace the VGAs... View full abstract»

• ### A 4-W Master–Slave Switching Amplitude Modulator for Class-E1 EDGE Polar Transmitters

Publication Year: 2008, Page(s):484 - 488
Cited by:  Papers (5)  |  Patents (1)
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For Class-E1 EDGE polar transmitters, we proposed a 4-W master-slave switching amplitude modulator (MS-SAM) for both high efficiency and wide bandwidth. It consists of a combination of two step-down modules with different switching frequencies and different switch sizes. The master module was designed for wide bandwidth and the slave module for high efficiency. The paper also presents a new curren... View full abstract»

• ### Sustained Slow-Scale Oscillation in Higher Order Current-Mode Controlled Converter

Publication Year: 2008, Page(s):489 - 493
Cited by:  Papers (31)
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DC-DC converters under current-mode control have been known to exhibit slow-scale oscillation as a result of a Hopf-type bifurcation as one or more of the parameters of the outer voltage loop are varied. In the absence of the outer voltage loop (i.e., open loop), slow-scale oscillation was generally not observed in simple low-order dc-dc converters, i.e., buck, buck-boost, and boost converters. In... View full abstract»

• ### Corrections to “Multiplierless, Folded 9/7–5/3 Wavelet VLSI Architecture” [Sep 07 770-774]

Publication Year: 2008, Page(s): 494
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In the above titled paper (ibid., vol. 54, no. 9, pp. 770-774, Sep. 07), equation (1) was incorrect. The correct equation is presented here. View full abstract»

## Aims & Scope

Part I will now contain regular papers focusing on all matters related to fundamental theory, applications, analog and digital signal processing. Part II will report on the latest significant results across all of these topic areas.

Full Aims & Scope

## Meet Our Editors

Editor-in-Chief

Chi K. Michael Tse
Dept. of Electronic and Information Engineering
Hong Kong Polytechnic University
Hunghom, Hong Kong
cktse@ieee.org