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Circuits and Systems II: Express Briefs, IEEE Transactions on

Issue 5 • Date May 2008

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Displaying Results 1 - 25 of 28
  • Table of contents

    Publication Year: 2008 , Page(s): C1 - C4
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  • IEEE Transactions on Circuits and Systems—II: Express Briefs publication information

    Publication Year: 2008 , Page(s): C2
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  • Design Considerations for Cascade \Delta \Sigma ADC's

    Publication Year: 2008 , Page(s): 389 - 393
    Cited by:  Papers (2)
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (279 KB) |  | HTML iconHTML  

    This brief discusses the design tradeoffs for cascaded delta-sigma (DeltaSigma) analog-to-digital converters. Increasing the order of the first loop allows a tradeoff between aggressive noise shaping and moderate operational transconductance amplifier (OTA) specifications. A comparison between fourth-order topologies indicates that for a cascade 3-1 topology, 55-dB OTA gain is sufficient for 96-dB signal-to-noise-distortion ratio while 5% coefficient mismatch results in less than 4-dB degradation. Dependent on the ratio between the power consumption of the digital recombination and decimation filter and that of the analog loop filter, the optimal topology can be chosen. A cascade 3-1 converter is most efficient when this ratio lies between 0.54 and 0.97. A design in a 65-nm CMOS technology demonstrates the performance of a cascade 3-1 converter. View full abstract»

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  • Current-Mode High-Accuracy High-Precision CMOS Amplifiers

    Publication Year: 2008 , Page(s): 394 - 398
    Cited by:  Papers (6)
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (279 KB) |  | HTML iconHTML  

    In low-voltage, deep sub- mum analog CMOS circuits, the accuracy and precision can be limited by the finite gain as well as by the input offset and 1/f noise voltages of opamps. Here, we show how to design high-accuracy high-precision CMOS amplifiers by properly applying dynamic element matching to a second-generation current conveyor (CCII); if all of the critical, nominally identical transistor pairs are dynamically matched, the resulting amplifier has low residual input offset and noise voltages. When compared with chopper or traditional dynamic element-matching amplifiers, the proposed approach alleviates the tradeoff between output swing and output resistance and is more robust against the finite opamp gain. Transistor-level simulations confirm theoretical results. View full abstract»

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  • A Wide-Band CMOS LC VCO With Linearized Coarse Tuning Characteristics

    Publication Year: 2008 , Page(s): 399 - 403
    Cited by:  Papers (15)  |  Patents (2)
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (819 KB) |  | HTML iconHTML  

    A pseudo-exponential capacitor bank structure is proposed to implement a wide-band CMOS LC voltage-controlled oscillator (VCO) with linearized coarse tuning characteristics. An octave bandwidth VCO employing the proposed 6-bit pseudo-exponential capacitor bank structure has been realized in 0.18-mum CMOS. Compared to a conventional VCO employing a binary weighted capacitor bank, the proposed VCO has considerably reduced the variations of the VCO gain (K VCO) and the frequency step per a capacitor bank code (f step/code) by 2.7 and 2.1 times, respectively, across the tuning range of 924-1850 MHz. Measurement results have also shown that the VCO provides the phase noise of - 127.1 dBc/Hz at 1-MHz offset for 1.752-GHz output frequency while dissipating 6 mA from a 1.8-V supply. View full abstract»

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  • A 50.8–53-GHz Clock Generator Using a Harmonic-Locked PD in 0.13- \mu m CMOS

    Publication Year: 2008 , Page(s): 404 - 408
    Cited by:  Papers (1)
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (1011 KB) |  | HTML iconHTML  

    A 50.8-53-GHz clock generator with a quadruplicate-harmonic-locked phase detector (PD) is presented to achieve a low spur and a low reference frequency. The proposed quadruplicate-harmonic-locked PD, a low-voltage Colpitts voltage-controlled oscillator, and a wide-range divide-by-2 divider are also presented. This clock generator has been fabricated in a 0.13-mum process. The measured reference spur is -59.88 dBc at 51.02 GHz with an input reference frequency of 199.3 MHz. The area is 0.93 mm times 1 mm with the on-chip loop filter and pads. It dissipates 87 mW without buffers from a 1.5-V supply. View full abstract»

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  • A 1-V CMOS Pseudo-Differential Amplifier With Multiple Common-Mode Stabilization and Frequency Compensation Loops

    Publication Year: 2008 , Page(s): 409 - 413
    Cited by:  Papers (1)
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (574 KB) |  | HTML iconHTML  

    This paper presents an operational amplifier for a 1-V supply voltage. It comprises three gain stages with ac-boosting and buffered Miller feedback compensation circuits. The implementation uses a standard 0.35-mum CMOS process ( V and V). To accommodate maximum voltage headroom between power rails, a pseudo-differential structure is adopted in this amplifier. The large common-mode gain associated with the structure is suppressed by two common-mode stabilization loops. The amplifier driving 100-pF loads achieves a 4.3-MHz gain-bandwidth product. The settling time of a 1- input step signal is 1.1s. The amplifier consumes 249 muW and occupies 0.06-mm silicon area. View full abstract»

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  • A Magnetic Feedback Method for Low-Voltage CMOS LNA Reverse-Isolation Enhancement

    Publication Year: 2008 , Page(s): 414 - 418
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (259 KB) |  | HTML iconHTML  

    A magnetic feedback method for enhancing the reverse isolation of low-voltage (1.2-V), single-transistor CMOS low-noise amplifiers (LNAs) is presented. The method neutralizes the gate-drain overlap capacitance of the amplifying transistor, allowing for adequate reverse isolation without gain reduction. The method does not require a differential LNA topology and input matching is facilitated since the degeneration inductor is not a part of a magnetic feedback loop. In addition, it allows for neutralizing the intrinsic part of the parasitic capacitance, which cannot be neglected in short-channel devices. Simulation results utilizing a standard 0.18-m CMOS process indicate a 17-29-dB improvement in the reverse-isolation performance with minimal noise figure deterioration. View full abstract»

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  • Physical Modeling of MEMS Variable Inductor

    Publication Year: 2008 , Page(s): 419 - 422
    Cited by:  Patents (1)
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (369 KB) |  | HTML iconHTML  

    In this study, we propose a new equivalent circuit model of variable inductors. We have proposed variable inductors with metal plate moving with a microelectromechanical system (MEMS) actuator. The proposed model consists of a conventional single-pi model, networks for silicon substrate and metal plate flowing eddy current, and coupling coefficients between these networks. The model is verified by fitting with measured data. Error in inductance and value is less than plusmn5%. View full abstract»

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  • Known-Plaintext Attack to Two Cryptosystems Based on the BB Equation

    Publication Year: 2008 , Page(s): 423 - 426
    Cited by:  Papers (4)
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (110 KB) |  | HTML iconHTML  

    Recently, Rama Murthy and Swamy proposed a symmetric cryptosystem based on the Brahmagupta-Bhaskara (BB) equation. The BB equation is the quadratic Diophantine equation nx 2 + k = y 2, where k is an integer and n is a positive integer such that radic(n) is irrational. For the particular case k=1, the equation is called the Pell equation. The proposed cryptosystem was modified later by the same authors in order to avoid the cryptanalysis given by Youssef. Below, a known-plaintext attack to both cryptosystems is presented. View full abstract»

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  • Strength-Reduced Parallel Chien Search Architecture for Strong BCH Codes

    Publication Year: 2008 , Page(s): 427 - 431
    Cited by:  Papers (7)
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (248 KB) |  | HTML iconHTML  

    The Chien search process is the most complex block in the decoding of Bose-Chaudhuri-Hochquenghem (BCH) codes. Since the BCH codes conduct the bit-by-bit error correction, they often need a parallel implementation for high throughput applications. The parallel implementation obviously needs much increased hardware. In this paper, we propose a strength reduced architecture for the parallel Chien search process. The proposed method transforms the expensive modulo-f(x) multiplications into shift operations, by which not only the hardware for multiplications but also that for additions are much reduced. One example shows that the hardware complexity is reduced by 90% in the implementation of binary BCH (8191, 7684, 39) code with the parallel factor of 64. Consequently, it is possible to achieve a speedup of 64 with only 13 times of the hardware complexity when compared with the serial processing. View full abstract»

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  • A 3 ,\times, 5-Gb/s Multilane Low-Power 0.18- \mu{\hbox {m}} CMOS Pseudorandom Bit Sequence Generator

    Publication Year: 2008 , Page(s): 432 - 436
    Cited by:  Papers (1)
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (550 KB) |  | HTML iconHTML  

    A low-power, three-lane, pseudorandom bit sequence (PRBS) generator has been fabricated in a 0.18-mum CMOS process to test a multilane multi-Gb/s transmitter that cancels far-end crosstalk. Although the proposed PRBS generator was designed to produce three uncorrelated 12-Gb/s PRBS sequences, measurement results included in this paper have been obtained at only 5 Gb/s due to test setup limitations. The prototype employs a CMOS latch optimized to operate at frequencies close to the of the process and a current-mode logic (CML) MUX with modified active inductor loads for better high-speed large-signal behavior. In order to reduce the power consumption, a quarter-clock rate linear feedback shift register (LFSR) core in a power-efficient parallel architecture has been implemented to minimize the use of power-hungry, high-speed circuitry. Further power reduction has been achieved through the clever partitioning of the system into static logic and CML. In addition, the prototype design produces three uncorrelated 12-Gb/s data streams from a single quarter-rate LFSR core, thereby amortizing the power across multiple channels which lowers the power per channel by 3 times. The total measured power consumption at 5 Gb/s is 131 mW per lane and the calculated figure of merit per lane is 0.84 pJ/bit, which is significantly better than previously published designs. View full abstract»

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  • CMOS Differential Logic Family With Conditional Operation for Low-Power Application

    Publication Year: 2008 , Page(s): 437 - 441
    Cited by:  Papers (1)
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (758 KB) |  | HTML iconHTML  

    In this paper, a set of CMOS differential logic circuits are introduced for use in low-power application. They perform a conditional operation for statistical power reduction during logic operation. The self-precharged version of the logic family provides additional power saving by allowing the use of a small-swing clock. Synchronous counters and bidirectional shift registers were designed in a 0.18-mum CMOS process technology to assess the performance of the proposed technique. The measurement results indicate that the counter with the proposed logic family achieves 50% power reduction compared with that of the conventional logic family. They also indicate that the shift registers with the proposed technique achieve 44%-63% power reduction at a typical switching activity of 0.25. View full abstract»

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  • Variable Digital Filter With Group Delay Flatness Specification or Phase Constraints

    Publication Year: 2008 , Page(s): 442 - 446
    Cited by:  Papers (5)
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (517 KB) |  | HTML iconHTML  

    In this paper, we consider the design of finite-impulse response variable digital filters (VDFs) with variable cutoff frequency or variable fractional delay. We propose the design of VDFs with minimum integral squared error and constraints on the maximum error deviation in conjunction with flatness group delay specification or phase constraints. These specifications allow the VDFs to have approximately linear phase, especially in the passband. As these specifications are required to be satisfied for all the filters generated by the VDF with controllable spectral characteristics, the linear constraints resulting from the flatness specification are relaxed to inequality constraints. To make the optimization problem tractable for the phase constrained problem, suitable approximations are employed in the paper. The design problem is formulated as an optimization problem with a quadratic cost function and infinite number of constraints. A numerical scheme with adaptive grid step size is proposed for solving the optimization problem. View full abstract»

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  • Design of Parallel Tomlinson–Harashima Precoders

    Publication Year: 2008 , Page(s): 447 - 451
    Cited by:  Papers (3)
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (179 KB) |  | HTML iconHTML  

    Like decision feedback equalizers (DFEs), Tomlinson-Harashima precoders (TH precoders) contain nonlinear feedback loops, which limit their use for high-speed applications. Unlike in DFEs, where the output levels of the nonlinear devices are finite, in TH precoders the output levels of the modulo devices are either infinite or finite but very large. Thus, it is difficult to apply look-ahead and pre-computation techniques to speed up TH precoders, which were successfully applied to design parallel and pipelined infinite impulse response (IIR) filters and DFEs in the past. However, a TH precoder can be viewed as an IIR filter with an input equal to the sum of the original input to the TH precoder and a finite-level compensation signal. Based on this point of view, a novel parallel architecture is proposed to speed up TH precoders. This architecture can be used in many high-speed applications, such as 10-Gb Ethernet over copper. View full abstract»

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  • A Fractionally Delaying Complex Hilbert Transform Filter

    Publication Year: 2008 , Page(s): 452 - 456
    Cited by:  Papers (4)
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (850 KB) |  | HTML iconHTML  

    In this paper, we present a novel complex discrete-time filter. This is a fractionally delaying (FD) Hilbert transform filter (HTF) further called the FD HTF. The filter is based on a pair of rotated variable fractional delay (VFD) filters. It is capable of performing the Hilbertian as well as VFD filtering of the incoming discrete-time signal at the same time. Thus, one can substitute a cascade of the HTF and the VFD filters with an aggregated filter proposed here. The technique is simple to implement. The advantages lie in lower total delay introduced by the compound filter and in a modular structure. The rotated VFD filters in the pair differ only in the value of one parameter - the VFD. The proposed FD HTF can be applied to adaptive quadrature sub-sample estimation of delay. View full abstract»

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  • Performance of an SIMO FM-DCSK Communication System

    Publication Year: 2008 , Page(s): 457 - 461
    Cited by:  Papers (18)
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (247 KB) |  | HTML iconHTML  

    A single-input multiple-output (SIMO) architecture of the frequency-modulated (FM) differential code-shift keying (DCSK) modulation technique is proposed. The new scheme employs orthogonal Walsh functions at the transmitter, with parallel substreams transmitted with a single antenna to help achieve a significant increase of the data rate. Multiple antennas are used at the receiver end to form an SIMO structure so as to obtain a diversity gain. Simulation results demonstrate that at a higher signal-to-noise ratio, the proposed SIMO FM-DCSK architecture has an outstanding bit error rate performance, in contrast to the direct-sequence (DS) vertical Bell Labs layered space-time (VBLAST) scheme that uses a complicated Rake receiver and minimum mean-square error detection, at the same data rate over multipath fading channels. In particular, the new scheme does not require any prior knowledge of the channel states, exact synchronization, and the complex Rake receiver, making the proposed algorithm simpler and yet more efficient than the DS-VBLAST scheme. View full abstract»

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  • A Note on PIN Polynomials and PRIN Rational Functions

    Publication Year: 2008 , Page(s): 462 - 463
    Cited by:  Papers (7)
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (70 KB) |  | HTML iconHTML  

    This brief presents a necessary and sufficient condition for testing positive, real, imaginary, and negative rational functions. A related term, the positive, imaginary, and negative polynomial, is defined and two necessary and sufficient conditions for testing it are given. View full abstract»

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  • Improvement of State Feedback Controller Design for Networked Control Systems

    Publication Year: 2008 , Page(s): 464 - 468
    Cited by:  Papers (25)
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (192 KB) |  | HTML iconHTML  

    A new method is proposed to improve the state feedback controller design for networked control systems (NCSs) taking both network-induced time delay and packet dropout into account in this paper. An appropriate Lyapunov functional is introduced to establish the improved sufficient stabilizability conditions for NCSs with memoryless state feedback controller by considering an additional useful term when estimating the upper bound of the derivative of Lyapunov functional and introducing new free weight matrices. Based on this less conservative existence condition, a networked controller design method is derived, which is equivalent to the solvability of a set of linear matrix inequalities. Numerical example is given to demonstrate the effectiveness and benefits of the proposed method. View full abstract»

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  • Networked Predictive Control Systems Based on the Hammerstein Model

    Publication Year: 2008 , Page(s): 469 - 473
    Cited by:  Papers (6)
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (165 KB) |  | HTML iconHTML  

    In this paper, a novel predictive control-based approach is proposed for a networked control system with random delays containing an input nonlinear process based on a Hammerstein model. The method uses a time-delay two-step generalized predictive control scheme, which consists of two parts: one is to deal with the input nonlinearity of the Hammerstein model and the other is to compensate for the network-induced delay in the networked control system. A theoretical result using the Popov criterion is presented for the closed-loop stability of the system in the case of a constant delay. Simulation examples illustrating the validity of the approach are also presented. View full abstract»

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  • All-MOS ASK Demodulator for Low-Frequency Applications

    Publication Year: 2008 , Page(s): 474 - 478
    Cited by:  Papers (4)
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (1417 KB) |  | HTML iconHTML  

    A miniature amplitude-shift-keying (ASK) demodulator without any passive elements, i.e., R or C, for low-frequency applications is presented in the paper. The noise margin of the envelope detector in the proposed ASK demodulator is enlarged such that any Schmitt trigger or current limiting resistor is no longer needed. It results in the number of transistors required for the ASK demodulator circuit is reduced to 12, while the area is merely 0.003025 mm2 using 0.35-mum 2P4M CMOS process. The power consumption is found to be 1.01 mW by physical measurement on silicon. The data rate is measured to be 250 kbps for 2-MHz carrier frequency and 27% modulation index. View full abstract»

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  • A Mixed-Signal Vector Modulator for Eigenbeamforming Receivers

    Publication Year: 2008 , Page(s): 479 - 483
    Cited by:  Papers (3)
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (301 KB) |  | HTML iconHTML  

    Analog vector modulators used in eigenbeamforming receivers usually include radio-frequency (RF) variable-gain amplifiers (VGAs) to modulate both the magnitude and the phase of receiving signals. The strenuous linearity requirement of RF VGAs makes it unsuitable to be realized in CMOS. This paper applies the mathematical concept of overcomplete expansion and coarse quantization to replace the VGAs with simple switches. The operation of these switches are controlled by an algorithm running in the digital domain. The proposed mixed-signal architecture thus shifts most of the system complexity from the analog domain to the digital domain. It will be shown that this architecture scales well with CMOS technology. View full abstract»

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  • A 4-W Master–Slave Switching Amplitude Modulator for Class-E1 EDGE Polar Transmitters

    Publication Year: 2008 , Page(s): 484 - 488
    Cited by:  Papers (4)  |  Patents (1)
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (1176 KB) |  | HTML iconHTML  

    For Class-E1 EDGE polar transmitters, we proposed a 4-W master-slave switching amplitude modulator (MS-SAM) for both high efficiency and wide bandwidth. It consists of a combination of two step-down modules with different switching frequencies and different switch sizes. The master module was designed for wide bandwidth and the slave module for high efficiency. The paper also presents a new current-sensing circuit based on a sample-and-hold circuit operable under a high switching frequency (40 MHz). We showed the topologies and operating principles. The chip was fabricated in a standard 0.35-m CMOS process with an area of 6.45 mm . The MS-SAM could drive the amplifiers of up to 4-W RF power in the experiment. We obtained an efficiency of 89%, and the converter's bandwidth was wide enough to meet the EDGE spectral requirements. View full abstract»

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  • Sustained Slow-Scale Oscillation in Higher Order Current-Mode Controlled Converter

    Publication Year: 2008 , Page(s): 489 - 493
    Cited by:  Papers (15)
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (448 KB) |  | HTML iconHTML  

    DC-DC converters under current-mode control have been known to exhibit slow-scale oscillation as a result of a Hopf-type bifurcation as one or more of the parameters of the outer voltage loop are varied. In the absence of the outer voltage loop (i.e., open loop), slow-scale oscillation was generally not observed in simple low-order dc-dc converters, i.e., buck, buck-boost, and boost converters. In this paper, slow-scale bifurcation in a higher order current-mode controlled converter is studied. It has been found experimentally that, even in the absence of a closed outer voltage loop, a current-mode controlled Cuk converter can exhibit a slow-scale Hopf-type bifurcation. The phenomenon was observed in a commercial low-ripple dc-dc converter which has been designed using the Cuk converter and the LM2611 controller. Such slow-scale oscillation of the inner current loop can also be observed in full-circuit SPICE simulations. An averaged model has been developed and implemented in SPICE to find the Hopf bifurcation boundaries. With this averaged model, the Hopf bifurcation can be explained conveniently using the traditional loop gain analysis. Specifically, the extra degrees of freedom in higher order dc-dc converters have opened up a new possible mode of instability which has not been found in simple low-order dc-dc converters. View full abstract»

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  • Corrections to “Multiplierless, Folded 9/7–5/3 Wavelet VLSI Architecture” [Sep 07 770-774]

    Publication Year: 2008 , Page(s): 494
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (26 KB) |  | HTML iconHTML  

    In the above titled paper (ibid., vol. 54, no. 9, pp. 770-774, Sep. 07), equation (1) was incorrect. The correct equation is presented here. View full abstract»

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Aims & Scope

TCAS II publishes brief papers in the field specified by the theory, analysis, design, and practical implementations of circuits, and the application of circuit techniques to systems and to signal processing. Included is the whole spectrum from basic scientific theory to industrial applications. The field of interest covered includes:

  • Circuits: Analog, Digital and Mixed Signal Circuits and Systems  
  • Nonlinear Circuits and Systems, Integrated Sensors, MEMS and Systems on Chip, Nanoscale Circuits and Systems, Optoelectronic
  • Circuits and Systems, Power Electronics and Systems
  • Software for Analog-and-Logic Circuits and Systems
  • Control aspects of Circuits and Systems. 

Full Aims & Scope