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IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems

Issue 12 • Date Dec 1992

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Displaying Results 1 - 8 of 8
  • A theory and implementation of sequential hardware equivalence

    Publication Year: 1992, Page(s):1469 - 1478
    Cited by:  Papers (51)  |  Patents (2)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (868 KB)

    A theory of sequential hardware equivalence is presented. This theory includes the notions of gate-level model (GLM), hardware finite state machine (HFSM), quotient machine, state equivalence (~), alignability, resetability, essential resetability, isomorphism, and sequential hardware equivalence. The theory is motivated by (1) the observation that it is impossible to control the initial state of ... View full abstract»

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  • A performance-aimed cell compactor with automatic jogs

    Publication Year: 1992, Page(s):1495 - 1507
    Cited by:  Papers (8)  |  Patents (2)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (1140 KB)

    To develop an efficient cell compactor for practical use, the authors take the one-dimensional compaction approach, but with a mixed symbolic and shape data model. A new algorithm of automatic jog generation is employed to create jogs, not only on critical paths but also on some noncritical paths. An optimum wire length minimization algorithm is used to tighten wires and polygon edges. These algor... View full abstract»

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  • An improved analytical short-channel MOSFET model valid in all regions of operating for analog/digital circuit simulation

    Publication Year: 1992, Page(s):1522 - 1528
    Cited by:  Papers (12)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (508 KB)

    An improved analytical model for short-channel MOSFETs which is valid in all regions of operation with both the continuous drain current and the output conductance by introducing a source-drain series resistance dependent scaling factor is proposed for analog/digital circuit simulation. This model considers all second-order effects for an accurate determination of the pinchoff point location witho... View full abstract»

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  • Restructuring WSI hexagonal processor arrays

    Publication Year: 1992, Page(s):1574 - 1585
    Cited by:  Patents (1)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (980 KB)

    A host-driven reconfiguration scheme, called HEX-REPAIR, is proposed for hexagonal processor arrays characterized by a large number of relatively simple cells. Such arrays have been shown to be the most efficient for many digital signal processing applications, such as matrix multiplication, and for some classes of filtering operations. Reconfiguration for these arrays is made difficult by the asy... View full abstract»

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  • A new global router using zero-one integer linear programming techniques for sea-of-gates and custom logic arrays

    Publication Year: 1992, Page(s):1479 - 1494
    Cited by:  Papers (7)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (1196 KB)

    A global routing method is proposed for sea-of-gates (SOG) arrays and custom logic arrays based on a zero-one linear integer programming technique. This method overcomes the various difficulties due to numerous physical constraints faced by many heuristic routing algorithms. In the proposed approach, all the physical constraints are rigorously modeled in the constraint equations. Alternatives for ... View full abstract»

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  • A new methodology for two-dimensional numerical simulation of semiconductor devices

    Publication Year: 1992, Page(s):1508 - 1521
    Cited by:  Papers (7)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (896 KB)

    A methodology for obtaining the self-consistent solution of semiconductor device equations discretized in the finite-difference scheme is proposed, in which a new discretized Green's function solution method is used to solve the two-dimensional discretized Poisson equation and a surface mapping technique is developed to treat arbitrary surface boundary conditions. The two-dimensional potential dis... View full abstract»

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  • Verified functions for generating signed-binary arithmetic hardware

    Publication Year: 1992, Page(s):1529 - 1558
    Cited by:  Papers (1)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (1764 KB)

    Formally verified metafunctions which synthesize array multipliers and inner product hardware of arbitrary size and structure are presented. The metafunctions operate on signed-binary inputs in general and two's-complement in particular, and are higher order. They are shown to be equivalence-preserving transformations and correctly produce multipliers and inner product hardware of arbitrary size a... View full abstract»

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  • Validatable nonrobust delay-fault testable circuits via logic synthesis

    Publication Year: 1992, Page(s):1559 - 1573
    Cited by:  Papers (23)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (1352 KB)

    The authors advocate a synthesis approach to delay-fault testing, wherein completely path-delay-fault testable circuits are automatically synthesized, meeting area and performance requirements. They give necessary and sufficient conditions for validatable nonrobust fault testability of paths in arbitrary multilevel networks. Validatable nonrobust testing as opposed to robust testing offers degrees... View full abstract»

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Aims & Scope

The purpose of this Transactions is to publish papers of interest to individuals in the area of computer-aided design of integrated circuits and systems composed of analog, digital, mixed-signal, optical, or microwave components.

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Meet Our Editors

Editor-in-Chief

VIJAYKRISHNAN NARAYANAN
Pennsylvania State University
Dept. of Computer Science. and Engineering
354D IST Building
University Park, PA 16802, USA
vijay@cse.psu.edu