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Circuits and Systems I: Regular Papers, IEEE Transactions on

Issue 3 • Date April 2008

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Displaying Results 1 - 25 of 31
  • Table of contents

    Page(s): C1 - C4
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    Freely Available from IEEE
  • IEEE Transactions on Circuits and Systems—I: Regular Papers publication information

    Page(s): C2
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  • Guest Editorial—ISCAS 2007

    Page(s): 713 - 714
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  • Low-Voltage Linearly Tunable CMOS Transconductor With Common-Mode Feedforward

    Page(s): 715 - 721
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (722 KB) |  | HTML iconHTML  

    This paper presents a new low-voltage pseudodifferential continuous-time CMOS transconductor for wide-band applications. The proposed cell is based on a feedforward cancellation of the input common-mode signal and keeps the input common mode voltage constant, while the transconductance is easily tunable through a continuous bias voltage. Linearity is preserved during the tuning process for a moderate range of transconductance values. Measurements results for a 0.35-m CMOS design show a 1:2 tuning range with total harmonic distortion figures at 10 MHz below 58 dB over the whole range up to a 200- differential output current. The proposed cell consumes less than 1.1 mW from a single 1.8-V supply. View full abstract»

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  • Process/Temperature Variation Tolerant Precision Signal Strength Indicator

    Page(s): 722 - 729
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    A receiving signal strength indicator (RSSI) built with transconductance amplifiers is presented. The RSSI achieves high tolerance to process/temperature variations by utilizing the unique nature of branch currents in a transconductance amplifier. These branch currents are used to implement a current-mode rectifier and amplitude clipping circuit that are tolerant of process variations. An on-chip offset control loop permits the entire RSSI to be realized with only one external component. In 0.18-mum CMOS with a 1.8 V supply, the RSSI draws 2.5 mA and provides 80 dB of offset suppression and more than 75 dB of log-linear range with less than +/ - 2-dB error due to process variation. View full abstract»

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  • A 12-Bit Ratio-Independent Algorithmic A/D Converter for a Capacitive Sensor Interface

    Page(s): 730 - 740
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    This paper describes a ratio-independent algorithmic analog-digital (A/D) converter architecture that is insensitive to capacitance ratio, amplifier offset voltage, amplifier input parasitics, and flicker noise. It requires only one differential amplifier, a dynamic latch, six capacitors, 36 switches, and some digital logic. The prototype 12-bit, 40-kS/s A/D converter (ADC) with an active die area of 0.041 mm2 is implemented in a 0.13-mum CMOS. The power dissipation is minimized using a dynamically biased operational amplifier. With a 68.4-muW power dissipation, the ADC achieves 80.2-dB spurious-free dynamic range and 63.3-dB signal-to-noise and distortion ratio. View full abstract»

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  • Cascaded Diophantine Frequency Synthesis

    Page(s): 741 - 751
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (470 KB) |  | HTML iconHTML  

    Cascaded diophantine frequency synthesis (CDFS) is an approach to high-resolution frequency synthesis based on the mathematical properties of integer numbers and diophantine equations. CDFS can be implemented using two or more phase-locked loops (PLLs) and frequency mixing stages in a cascade topology. CDFS achieves frequency resolution arbitrarily finer than that of the constituent PLLs while maintaining their loop bandwidths and frequency hopping agility. CDFS results in intermediate signals with minimal frequency ranges in all frequency mixing stages, allowing for improved spectral purity and lower design complexity compared to the parallel form of its predecessor, diophantine frequency synthesis (DFS). CDFS architectures are modularly structured and expandable. The paper introduces CDFS focusing on the mathematical and algorithmic aspects. View full abstract»

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  • Desensitized CMOS Low-Noise Amplifiers

    Page(s): 752 - 765
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (1473 KB) |  | HTML iconHTML  

    The minimum attainable noise figure for scaled- CMOS low-noise amplifiers (LNAs) is limited by impedance mismatches such as the well-known noise/power tradeoff. In this paper, we show that a power-constrained optimization of the device noise resistance parameter, Rn, significantly reduces the impact of mismatches and variations and leads to an almost simultaneous noise and power match. This process, called desensitization, makes the design largely immune to measurement and modeling errors and manufacturing variations, and significantly reduces frequency-dependent noise mismatches in wide-band LNAs. Measured data from devices and desensitized LNAs designed on 180-nm and 90-nm CMOS processes shows that: (1) a device size selected for optimum Rnmiddot is less sensitive to source impedance mismatches and provides a wide-band noise match; and (2) LNAs approach a simultaneous input and noise match, and exhibit significant improvements (ges 2x) in their wide-band noise performance. View full abstract»

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  • Design of a High-Speed Differential Frequency-to-Voltage Converter and Its Application in a 5-GHz Frequency-Locked Loop

    Page(s): 766 - 774
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    This paper presents a new algorithm and circuit implementation for high-speed frequency-to-voltage converters (FVC). The proposed system overcomes the deficiencies of a previously reported converter and can operate about 20 times faster. To validate this FVC and show its usefulness, it was used in the design of a frequency locked loop. For the design of this loop, it was found that existing analytical models were incomplete in that they neglect the delay associated to frequency measurements. We proposed a new model which, unlike previous work, shows that frequency locked loops can potentially be unstable. Simulations confirm this fact and also show that the proposed implementation can operate at 5 GHz. To validate the results, a prototype circuit has been fabricated in a 0.18-mum CMOS technology. Tests performed on the prototype show that it runs reliably at 3.84 GHz and consumes 77.4 mW with a 1.8-V power supply when biasing circuitry is included. View full abstract»

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  • Continuous-Time Sigma–Delta Modulator With an Embedded Pulsewidth Modulation

    Page(s): 775 - 785
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    A new Continuous-Time (CT) sigma-delta modulator (SDM) based on the well-known asynchronous SDM is proposed in this paper. To this end, the flash quantizer and the digital-to-analog converter (DAC) in a multibit (MB) CT-SDM clocked at a rate fmax are replaced by a single-bit (SB) comparator with hysteresis clocked at a higher rate fs and a SB-DAC, respectively. By proper selection of the hysteresis in the comparator and the ratio F = fs/fmax, the performances of both modulators are shown to be equivalent. The comparator with hysteresis and the loop filter produce, in the modulator output, a limit cycle of frequency /max which is modulated by the input signal. Therefore, the modulator output can be considered to be a pulsewidth (PW) modulated signal with a frequency approximately equal to /max, and the proposed modulator is called a PW-SDM. Despite the high sampling rate of the comparator output, the integrators and the SB-DAC of the proposed modulator have the same speed requirements as those of the equivalent conventional MB-SDM. On the other hand, in the proposed modulator there are not MB (analog-to-digital or digital-to-analog) converters. Therefore, for a given set of specifications, the proposed PW-SDM is expected to consume less power and area than its equivalent conventional MB modulator. View full abstract»

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  • A Bandpass Filter With Inherent Gain Adaptation for Hearing Applications

    Page(s): 786 - 795
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    In this paper, we propose a novel bandpass filter design that incorporates automatic gain control (AGC). The gain control in the filter reduces the performance requirements of a wide-band AGC, and allows for low-power multichannel compression. The filter achieves up to 15 dB of compression on a 55-dB input dynamic range and is tunable over the audio frequency range, with microwatt power consumption and <5% harmonic distortion. View full abstract»

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  • A 5-Gb/s CDR Circuit With Automatically Calibrated Linear Phase Detector

    Page(s): 796 - 803
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (1743 KB) |  | HTML iconHTML  

    This paper presents a 5-Gb/s clock and data recovery (CDR) circuit which implements a calibration circuit to correct static phase offsets in a linear phase detector. Static phase offsets directly reduce the performance of CDR circuits as the incoming data is not sampled at the center of the eye. Process nonidealities can cause static phase offsets in linear phase detectors by adversely affecting the circuits in a way which is difficult to design for, making calibration an attractive solution. Both the calibration algorithm and test chip implementation are described and measured results are presented. The CDR circuit was fabricated in a 0.18-mum, six metal layer standard CMOS process. With a pseudorandom bit sequence of 27 - 1 calibration improved the measured bit error rate from 4.6 x 10-2 to less than 10-13. View full abstract»

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  • A Robust and Scalable Constant- g_m Rail-to-Rail CMOS Input Stage With Dynamic Feedback for VLSI Cell Libraries

    Page(s): 804 - 816
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    In this paper, we propose a robust and scalable constant- rail-to-rail CMOS input stage for VLSI cell libraries. The proposed circuit does not rely on the characteristics and particular operation (strong, moderate, and weak inversion) regions of the input transistors and is insensitive to mismatches between p- and n-channel devices. Only standard CMOS transistors are used in the circuit without any special devices, such as floating-gate or depletion-mode transistors. Very small variations (less than ) have been achieved without sacrificing the large-signal behavior. The proposed circuit is proven effective for both long-channel and deep sub-micron CMOS technologies and is suitable for VLSI cell libraries, audio/video, embedded mixed-signal system-on-chip (SoC), and other applications. A prototype amplifier with rail-to-rail input common-mode range has been designed and fabricated in a standard 0.35-m CMOS technology. Experimental results confirm the effectiveness and robustness of proposed techniques. View full abstract»

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  • Cascaded Complex ADCs With Adaptive Digital Calibration for I/Q Mismatch

    Page(s): 817 - 827
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (1459 KB) |  | HTML iconHTML  

    A complex analog-to-digital converter (ADC) intended for digital intermediate frequency (IF) receiver applications digitizes analog signals at IFs with excellent power/bandwidth efficiency. However, it is vulnerable to mismatches between its in-phase and quadrature (I/Q) paths that can dramatically degrade its performance. The proposed solution mitigates I/Q mismatch effects using a complex sigma-delta (SigmaDelta) modulator cascaded with 9-bit pipeline converters in each of the I and Q paths. The quantization noise of the first stage complex modulator is eliminated using an adaptive scheme to calibrate finite-impulse response digital filters in the digital noise-cancellation logic block. Although low-pass SigmaDelta cascade ADCs are widely used because of their inherent stability and high-order noise shaping, the complex bandpass cascade architecture introduced herein maintains these advantages and doubles the noise shaping bandwidth. Digital calibration also reduces the effects of analog circuit limitations such as finite operational amplifier gain, which enables high performance and low power consumption with high-speed deep-submicrometer CMOS technology. Behavioral simulations of the complex SigmaDelta/pipeline cascade bandpass ADC using the adaptive digital calibration algorithm predict a signal-to-noise ratio (SNR) of 78 dB over a 20-MHz signal bandwidth at a sampling rate of 160 MHz in the presence of a 1% I/Q mismatch. View full abstract»

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  • Arithmetic Unit for Finite Field {\rm GF}(2^{m})

    Page(s): 828 - 837
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    An arithmetic unit (AU) that performs all basic arithmetic operations in the finite field GF(2m) is presented, where m is an arbitrary integer. The presented finite field AU consists of an arithmetic processor, an arithmetic logic unit, and a control unit. The proposed AU has low circuit complexity and is programmable, so that any error-correcting decoder that operates in GF(2m) can be easily implemented with this AU. View full abstract»

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  • Beamforming of Broad-Band Bandpass Plane Waves Using Polyphase 2-D FIR Trapezoidal Filters

    Page(s): 838 - 850
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    A new discrete-domain method is proposed for the beamforming of temporally broad-band bandpass plane waves (PWs) using a real-coefficient 2-D spatio-temporal (ST) finite-impulse response (FIR) filter having a novel rectangularly symmetric double-trapezoidal-shaped passband. The arriving temporally broad-band-bandpass ST PWs are received by a 1-D uniformly distributed sensor array. The sensor signals are pre-filtered, down-shifted to the intermediate frequency (IF) band, low-pass filtered and synchronously sampled by the real IF tri-stage temporal sampler array, resulting in a real-valued 2-D sampled sequence. The beamforming operation is then carried out on this 2-D sampled sequence using the real-coefficient 2-D FIR double-trapezoidal filter. Arithmetic complexity in the hardware implementation of the 2-D FIR double-trapezoidal filter is significantly reduced by using an array of real-coefficient polyphase 1-D FIR filters. Experimental results have confirmed that this method is capable of enhancing the desired temporally broad-band-bandpass ST PWs according to their directions of arrival under severe co-channel interference. View full abstract»

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  • Perfect Blind-Channel Shortening for Multicarrier Systems

    Page(s): 851 - 860
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    In multicarrier systems, when the order of a channel impulse response is larger than the length of the cyclic prefix (CP), there is a significant performance degradation due to interblock interference (IBI). This paper proposes a blind-channel shortening method in which the equalizer parameter vector is formed by the noise subspace of the received signal correlation matrix so that the output power is maximized. The proposed method can not only shorten the effective channel impulse response to within the CP length but also maximize the output signal-to-interference-and-noise ratio while eliminating the IBI. We point out that the performance depends on the choice of a decision delay and propose a simple method for determining the appropriate delay. We propose both a batch algorithm and an adaptive algorithm and show by simulation that they are superior to the conventional algorithms. View full abstract»

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  • Fully Digital Random Bit Generators for Cryptographic Applications

    Page(s): 861 - 875
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    This paper is devoted to the analysis, implementation, and modeling of fully digital random bit generators based on recent research results on the design of stateless oscillator-based generators. A new approach to the data quality test is adopted where, instead of passing bunches of statistical tests on the raw data, the focus is on the verification of a minimum entropy limit for the delivered random numbers after the digital post-processing. The architecture of the proposed generator (noise source and post-processing algorithm) is described in detail and experimental results in a 90-nm CMOS process are reported. The fabricated device reaches a throughput of 1.74 Mb/s after post-processing with an area of 13000 mum2 and a power consumption of about 240 muW when running at its maximum speed. A statistical model for the noise source is provided and the entropy of the post-processed data has been evaluated obtaining an entropy per byte higher than 7.999. View full abstract»

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  • Phase-Shift-Free M -Phase Spreading Sequences of Markov Chains

    Page(s): 876 - 882
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    We consider the optimum spreading sequences of Markov chains in terms of the mean value of the limit of variance of the normalized multiple-access interference for asynchronous spread-spectrum multiple access communication systems. We first define a novel class of spreading sequences, namely the phase-shift-free M(ges 3)-phase spreading sequences. Then we theoretically and experimentally show that the optimum phase-shift-free M-phase spreading sequences of Markov chains are superior to the optimum binary spreading sequences of Markov chains in terms of the bit-error probabilities based on the central limit theorem for periods N > 5. View full abstract»

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  • Chaotic Synchronization Using Sampled-Data Fuzzy Controller Based on Fuzzy-Model-Based Approach

    Page(s): 883 - 892
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (478 KB) |  | HTML iconHTML  

    This paper presents the synchronization of chaotic system using a sampled-data fuzzy controller. To carry out the system analysis, a fuzzy model is employed to represent the chaotic systems. Linear-matrix-inequality (LMI)-based system stability and performance conditions are derived using a Lyapunov-based approach. The derived LMI-based stability and performance conditions are employed to aid the design of a stable and well-performing sampled-data fuzzy controller to achieve the synchronization of chaotic systems. An application example is given to illustrate the merits of the proposed approach. View full abstract»

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  • Synchronization of Chaotic Systems Using Time-Delayed Fuzzy State-Feedback Controller

    Page(s): 893 - 903
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    This paper presents the fuzzy-model-based control approach to synchronize two chaotic systems subject to parameter uncertainties. A fuzzy state-feedback controller using the system state of response chaotic system and the time-delayed system state of drive chaotic system is employed to realize the synchronization. The time delay which complicates the system dynamics makes the analysis difficult. To investigate the system stability and facilitate the design of fuzzy controller, Takagi-Sugeno (T-S) fuzzy models are employed to represent the system dynamics of the chaotic systems. Furthermore, the membership grades of the T-S fuzzy models become uncertain due to the existence of parameter uncertainties which further complicates the system analysis. To ease the stability analysis and produce less conservative analysis result, the membership functions of both T-S fuzzy models and fuzzy controller are considered. Stability conditions are derived using Lyapunov-based approach to aid the design of fuzzy state-feedback controller to synchronize the chaotic systems. Simulation examples are presented to illustrate the merits of the proposed approach. View full abstract»

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  • Template Design for Cellular Nonlinear Networks With 1-Bit Weights

    Page(s): 904 - 913
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    In this paper, we show how a cellular nonlinear network with 1-bit weight programmability can be used for processing black and white image data. When using such a binary-programmable network, some templates need to be processed algorithmically, in other words, divided into subtasks that are processed consecutively. We classify templates into groups based on their properties and give guidelines as to how the division into subtasks (when applicable) is performed. A large collection of templates suitable for the proposed model is shown. We also describe one possible cell structure that realizes the binary-programmable model. The cell is modeled with Matlab and selected template simulations are shown. View full abstract»

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  • On-Chip Power-Grid Simulation Using Latency Insertion Method

    Page(s): 914 - 931
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    Ensuring the integrity of the power supply in the power distribution networks (PDNs) of a chip is essential for building reliable high-performance chips. To ensure the power integrity, accurate, and memory- and time-efficient simulation approaches for simulating the power-supply noise in the on-chip PDN are essential. In this paper, a finite-difference formulation based on the latency insertion method (LIM) has been employed for simulating the power-supply noise in the on-chip PDN. A new common-mode type equivalent circuit has been proposed. In this equivalent circuit, a capacitance to ideal ground may not be present at all the nodes. Further, the nodes can be capacitively coupled to each other. To avoid inverting a large nonbanded matrix, a small capacitance to ground is added to a node that did not have any capacitance to ground, and a small series inductance is added to any floating capacitor that did not have any series inductance. Approximate closed-form expressions to compute the values of these capacitances to ground and series inductances have been proposed. The accuracy of the LIM-enabled transient simulation and the accuracy of the proposed closed-form expressions have been demonstrated. The memory and time complexity of the simulation for each time step have been shown to be O(Nn) each, where Nn is the number of nodes in the equivalent circuit. Stability condition is derived for the first time for multidimensional inhomogeneous RLC circuit. A upper bound of the time step is derived from the stability condition. Using this bound on the time step, the runtime of the overall transient simulation has been estimated to be approximately proportional to Nn 2-2.5 for Nn in the order of millions. View full abstract»

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  • Control of a Planar System With Quantized and Saturated Input/Output

    Page(s): 932 - 942
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    The stabilization problem for a simple (unstable) planar system in the presence of input and output quantization and saturation is addressed. It is shown that global stability to a terminal set, the size of which can be arbitrarily reduced, is achieved by means of a hybrid output feedback control law, which reads out the plant only three values and delivers a control action composed of three values. Directions to extend the proposed results to a class of -dimensional systems are also provided. Simulation results complete the work. View full abstract»

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  • Estimation of Carrier Frequency Offset With I/Q Mismatch Using Pseudo-Offset Injection in OFDM Systems

    Page(s): 943 - 952
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (1176 KB) |  | HTML iconHTML  

    This work presents a novel carrier frequency offset (CFO) estimation algorithm, based on pseudo-CFO (P-CFO), to estimate the CFO value under the conditions of I/Q mismatch for direct conversion structures with 2-dB gain error and 20-deg. phase error in frequency selective fading channels. To circumvent CFO with I/Q mismatch, the proposed P-CFO algorithm rotates three training symbols by adding extra frequency offset into the received sequence to improve CFO estimation. Simulation results indicate that the estimation error of the proposed method is about 0.3 ppm, which is lower than those of two-repeat preamble-based methods. Additionally, the proposed P-CFO algorithm is compatible with the conventional method, and is appropriate for SoC implementation. The proposed scheme is implemented as part of an orthogonal frequency-division multiplexing wireless receiver fabricated in a 0.13-mum CMOS process with 3.3 times 0.4 mm2 core area and 10-mW power consumption at 54-Mbits/s data rate. View full abstract»

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Aims & Scope

The theory, analysis, design, and practical implementations of circuits, and the application of circuit techniques to systems and to signal processing.

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Meet Our Editors

Editor-in-Chief
Shanthi Pavan
Indian Institute of Technology, Madras