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IEE Proceedings E - Computers and Digital Techniques

Issue 6 • Date Nov 1992

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Displaying Results 1 - 8 of 8
  • Rational sampling rate conversion structures with minimum delay requirements

    Publication Year: 1992, Page(s):477 - 485
    IEEE is not the copyright holder of this material | Click to expandAbstract | PDF file iconPDF (452 KB)

    Recent developments on multirate system design show that a rational (L/M) sampling rate conversion system can be reconfigured into a three-dimensional polyphase structure. However, the delay requirements associated with each subfilter path in such a structure have not sufficiently been considered. The paper presents a detailed analysis of the delay requirements, and shows that a reduction by a fac... View full abstract»

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  • VLSI implementation of mod-p multipliers using homomorphisms and hybrid cellular automata

    Publication Year: 1992, Page(s):486 - 490
    IEEE is not the copyright holder of this material | Click to expandAbstract | PDF file iconPDF (324 KB)

    The VLSI implementation of mod-p multipliers, where p is prime, using homomorphisms and one-dimensional hybrid cellular automata (HCA) is presented. This new technique uses the maximum-length cycle produced by HCA, to realise implementation using the minimum possible number of cells in the array. A new theorem on homomorphisms shows how a cyclic group can be mapped into a state group of HCA, of sm... View full abstract»

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  • Cellular automata based pattern generator for testing RAM

    Publication Year: 1992, Page(s):469 - 476
    IEEE is not the copyright holder of this material | Click to expandAbstract | PDF file iconPDF (488 KB)

    Presents a new strategy for parallel testing of RAM. A cellular automata (CA) based test pattern generator for detecting pattern sensitive faults (PSFs) in random access memories is also reported. An eight-cell one dimensional three neighbourhood CA has been extended to the five-neighbourhood case preserving the criterion of local connections. By changing the neighbourhood relation, all the 64 pat... View full abstract»

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  • Multiple valued input generalised Reed-Muller forms

    Publication Year: 1992, Page(s):519 - 527
    IEEE is not the copyright holder of this material | Click to expandAbstract | PDF file iconPDF (552 KB)

    The concept of canonical multiple valued input generalised Reed-Muller (MIGRM) forms is introduced. The MIGRM is a direct extension of the well known generalised Reed-Muller (GRM) forms to the logic with multiple valued inputs. The concept of the polarity of a GRM form is generalised to the polarity matrix of a MIGRM form. A tabular pattern-matching method is presented for the calculation of a MIG... View full abstract»

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  • Simplification of switching functions expressed in Reed-Muller algebraic form

    Publication Year: 1992, Page(s):511 - 518
    Cited by:  Papers (1)
    IEEE is not the copyright holder of this material | Click to expandAbstract | PDF file iconPDF (476 KB)

    The simplification of switching functions expressed as modulo-2 sums of products is investigated. It is demonstrated that the apparently different approaches of general simplification and the location of the optimum canonical representation of a given function are ultimately equivalent providing the complete range of possible canonical forms is considered. An extended form of function vector is in... View full abstract»

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  • Message-efficient distributed mutual exclusion incorporating the 'least recently used' fairness criterion

    Publication Year: 1992, Page(s):501 - 504
    Cited by:  Papers (1)
    IEEE is not the copyright holder of this material | Click to expandAbstract | PDF file iconPDF (320 KB)

    The fairness criterion is a crucial attribute of distributed mutual exclusion algorithms. This criterion determines for how long a node, which has issued a request for executing a critical section, has to wait. All solutions to the distributed mutual exclusion problem are expected to be starvation free. Ensuring starvation freedom alone may not be sufficient in large distributed systems with onlin... View full abstract»

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  • VLSI module for high-performance multiply, square root and divide

    Publication Year: 1992, Page(s):505 - 510
    Cited by:  Papers (1)
    IEEE is not the copyright holder of this material | Click to expandAbstract | PDF file iconPDF (384 KB)

    A high-performance VLSI architecture to perform multiply-accumulate, division and square root operations is proposed. The circuit is highly regular, requires only minimal control and ean be pipelined right down to the bit level. The system can also be reconfigured on every cycle to perform any one of these operations. The gate count per row has been estimated at (27n+70) gate equivalents where n i... View full abstract»

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  • Efficient state reduction methods for PLA-based sequential circuits

    Publication Year: 1992, Page(s):491 - 500
    IEEE is not the copyright holder of this material | Click to expandAbstract | PDF file iconPDF (652 KB)

    Experiences with heuristics for the state reduction of finite-state machines are presented and two new heuristic algorithms described in detail. Results on machines from the literature and from the MCNC benchmark set are shown. The area of the PLA implementation of the combinational component and the design time are used as figures of merit. The comparison of such parameters, when the state reduct... View full abstract»

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