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# IEEE Transactions on Electron Devices

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Displaying Results 1 - 25 of 27

Publication Year: 2008, Page(s):C1 - C4
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• ### IEEE Transactions on Electron Devices publication information

Publication Year: 2008, Page(s): C2
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• ### Power Density and Efficiency of Thermophotovoltaic Energy Conversion Using a Photonic-Crystal Emitter and a $hbox{2}$ -D Metal-Grid Filter

Publication Year: 2008, Page(s):1101 - 1108
Cited by:  Papers (7)
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Three-dimensional metallic photonic crystals have been suggested to be ideal candidates for thermal emitters in thermophotovoltaic energy conversion systems due to their high emission power in the allowed passband and also their emission suppression in the long-wavelength tail. In this paper, calculations were performed to compare a photonic-crystal emitter and a blackbody emitter in the thermodyn... View full abstract»

• ### A Comparison of the Performance and Stability of ZnO-TFTs With Silicon Dioxide and Nitride as Gate Insulators

Publication Year: 2008, Page(s):1109 - 1115
Cited by:  Papers (70)
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The performance and stability of thin-film transistors with zinc oxide as the channel layer are investigated using gate bias stress. It is found that the effective channel mobility, ON/OFF ratio, and subthreshold slope of the devices that incorporate SiN are superior to those with SiO2 as the dielectric. The application of positive and negative stress results in the device transfer char... View full abstract»

• ### Band-Structure Effects on the Performance of III–V Ultrathin-Body SOI MOSFETs

Publication Year: 2008, Page(s):1116 - 1122
Cited by:  Papers (29)
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This paper examines the impact of band structure on deeply scaled III-V devices by using a self-consistent 20-band -SO semiempirical atomistic tight-binding model. The density of states and the ballistic transport for both GaAs and InAs ultrathin-body n-MOSFETs are calculated and compared with the commonly used bulk effective mass approximation, including all the valleys (, , and ). Our results sh... View full abstract»

• ### A Method for Current Spreading Analysis and Electrode Pattern Design in Light-Emitting Diodes

Publication Year: 2008, Page(s):1123 - 1128
Cited by:  Papers (39)  |  Patents (2)
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We successfully developed a 3D electrical circuit model consisting of resistances and intrinsic diodes to analyze the current spreading effect in an InGaN/GaN multiple-quantum-well light-emitting diode. Each circuit element was formulated by physical parameters such as structural dimensions or material properties. We obtained a good agreement between the measured 2D light intensity distribution em... View full abstract»

• ### New Sustain Waveform for Improving Luminous Efficiency in Wide-Gap Plasma-Display Panel

Publication Year: 2008, Page(s):1129 - 1136
Cited by:  Papers (6)
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The three-electrode microdischarge characteristics of ac-plasma-display panels (PDPs) are analyzed with a wide sustain discharge gap of 180 mum. In particular, the luminous efficiency variation is examined as a parameter of the operating frequency. It is found that the luminous efficiency decreases with an increase in the operating frequency. In other words, a failure discharge mode for luminous e... View full abstract»

• ### Anomalous Hot-Carrier-Induced Increase in Saturation-Region Drain Current in n-Type Lateral Diffused Metal–Oxide–Semiconductor Transistors

Publication Year: 2008, Page(s):1137 - 1142
Cited by:  Papers (9)
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Anomalous increase in saturation-region drain current Id(sat) but serious on-resistance degradation (decrease in linear-region drain current) is observed in n-type high-voltage lateral diffused MOS transistors stressed under medium gate voltage Vg. However, Id(sat) is degraded for the devices stressed under low and high Vg. Experimental data reveal that ... View full abstract»

• ### Optimization of Gate Leakage and NBTI for Plasma-Nitrided Gate Oxides by Numerical and Analytical Models

Publication Year: 2008, Page(s):1143 - 1152
Cited by:  Papers (6)
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Reduction in static-power dissipation (gate leakage) by using nitrided oxides comes at the expense of enhanced negative-bias temperature instability (NBTI). Therefore, determining the nitrogen content in gate oxides that can simultaneously optimize gate-leakage and NBTI degradation is a problem of significant technological relevance. In this paper, we experimentally and theoretically analyze wide ... View full abstract»

• ### Reliability Mechanisms of LTPS-TFT With $hbox{HfO}_{2}$ Gate Dielectric: PBTI, NBTI, and Hot-Carrier Stress

Publication Year: 2008, Page(s):1153 - 1160
Cited by:  Papers (22)
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In this paper, a comprehensive study of the reliability mechanisms of high-performance low-temperature polycrystalline-Si thin-film transistor (LTPS-TFT) with gate dielectric is reported for the first time. Various bias- and temperature-stress conditions, which correspond to positive-bias stress (PBS), positive-bias temperature instability (PBTI), negative-bias stress (NBS), negative-bias temperat... View full abstract»

• ### Optimal Dual-$V_{T}$ Design in Sub-100-nm PD/SOI and Double-Gate Technologies

Publication Year: 2008, Page(s):1161 - 1169
Cited by:  Papers (1)  |  Patents (2)
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Dual-threshold-voltage (VT) CMOS is an effective way to reduce leakage power in high-performance very-large-scale-integration circuits. In this paper, we explore the technology design space for dual-threshold-voltage transistor design in deep-sub-100-nm technology nodes. We propose a technique of achieving high-VT (HVT) devices using thicker gate-sidewall offset spacers to in... View full abstract»

• ### Evaluation of Transmission Line Model Structures for Silicide-to-Silicon Specific Contact Resistance Extraction

Publication Year: 2008, Page(s):1170 - 1176
Cited by:  Papers (18)  |  Patents (1)
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In order to measure silicide-to-silicon specific contact resistance rhoc, transmission line model (TLM) structures were proposed as attractive candidates for embedding in CMOS processes. We optimized TLM structures for nickel silicide and platinum silicide and evaluated them for various doping levels of n- and p-type Si. The measurement limitations and accuracy of the specific contact r... View full abstract»

• ### Analysis of the Effects of Fringing Electric Field on FinFET Device Performance and Structural Optimization Using 3-D Simulation

Publication Year: 2008, Page(s):1177 - 1184
Cited by:  Papers (17)
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In this paper, the potential impact of parasitic capacitance resulting from fringing field on FinFET device performance is studied in detail using a 3-D simulator implemented with quantum-mechanical models. It was found that fringing field from gate to source contributes significantly to FinFET performance and speed. The strength of fringing field is closely related to device features such as gate... View full abstract»

• ### Sub-$hbox{100-}muhbox{A}$ Reset Current of Nickel Oxide Resistive Memory Through Control of Filamentary Conductance by Current Limit of MOSFET

Publication Year: 2008, Page(s):1185 - 1191
Cited by:  Papers (66)  |  Patents (2)
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Resistive random access memory consisting of NiO resistive memories and control transistors was fabricated with 0.18-mum CMOS technology. An initial forming voltage as low as 2 V was achieved with thin NiO film, and a reset current lower than 100 muA was realized by using the current limit of a selected cell transistor in the set process (1T-1R). The current level was determined by its gate voltag... View full abstract»

• ### RF Small-Signal Analysis of Schottky-Barrier p-MOSFET

Publication Year: 2008, Page(s):1192 - 1202
Cited by:  Papers (23)
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This paper presents a detailed RF study for source/drain Schottky-barrier (SB) MOSFETs. Using on-wafer -parameters, high-frequency (HF) figures-of-merit (FoMs) and small-signal equivalent circuits (SSEC) are first extracted and discussed for a -gate-length SB MOSFET. Then, using ac simulations, HF FoM's sensitivity along SB height and underlap length variations are subsequently presented. The whol... View full abstract»

• ### Investigation of Thermal Noise in UTB GOI and SOI Devices

Publication Year: 2008, Page(s):1203 - 1210
Cited by:  Papers (2)
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The thermal-noise performances of ultrathin-body silicon-on-insulator (SOI) and germanium-on-insulator (GOI) devices are investigated and compared through simulation in this paper. The figures-of-merit for noise characteristics are considered in terms of the minimum of noise figure (NFmin)and equivalent noise resistance (Rn). GOI devices exhibit better noise performance over ... View full abstract»

• ### Experimental Characterization of the Vertical Position of the Trapped Charge in Si Nitride-Based Nonvolatile Memory Cells

Publication Year: 2008, Page(s):1211 - 1219
Cited by:  Papers (34)
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We present a broad set of experiments on silicon nitride-based memories aimed at the investigation of the vertical position of the charge trapped in the nitride layer of silicon-oxide-nitride-oxide-semiconductor (SONOS) memories during program and erase in the tunneling regime. The results obtained for SONOS devices with conventional oxide-nitride-oxide and oxide-nitride-oxide-nitride-oxide gate s... View full abstract»

• ### Charge Collection From Within a Collecting Junction Well

Publication Year: 2008, Page(s):1220 - 1228
Cited by:  Papers (7)
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This paper provides the analytical equation for the charge collection from a collecting region with a finite dimension. Electron-beam-induced current has widely been used for semiconductor characterization. The availability of analytical expressions would further enhance the study and development of various measurement techniques. Nevertheless, most devices are fabricated with junctions that have ... View full abstract»

• ### Lateral Current Confinement Determines Silicon Avalanche Transistor Operation in Short-Pulsing Mode

Publication Year: 2008, Page(s):1229 - 1236
Cited by:  Papers (5)
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The transient in a Si bipolar junction transistor was investigated in high-current short-pulsing ( 2 ns) mode both experimentally and numerically. A comparison of measured and simulated waveforms clearly showed that only a small fraction of the perimeter of the emitter-base interface (in the lateral direction) takes part in the switching transient when a capacitor of relatively small value (80 pF)... View full abstract»

• ### Thin-Film Bulk-Acoustic-Resonator Gas Sensor Functionalized With a Nanocomposite Langmuir–Blodgett Layer of Carbon Nanotubes

Publication Year: 2008, Page(s):1237 - 1243
Cited by:  Papers (37)
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A thin-film bulk acoustic resonator (TFBAR) based on a vibrating membrane of AlN/Si3N4 has been fabricated onto a silicon substrate and functionally characterized as gas sensor at a resonating frequency of 1.045 GHz. This novel TFBAR-based gas sensor has been functionalized by a sensing nanocomposite layer, prepared by a Langmuir-Blodgett (LB) technique, of single-walled carb... View full abstract»

• ### (111)-Faceted Metal Source and Drain for Aggressively Scaled Metal/High- $k$ MISFETs

Publication Year: 2008, Page(s):1244 - 1249
Cited by:  Papers (15)
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We have proposed a (111)-faceted metal source and drain (S/D) with a metal gate and a high-k gate dielectric for aggressively scaled complementary metal-insulator-semiconductor field-effect transistors (MISFETs). The metal S/D is formed by epitaxially grown nickel disilicide. N-type or p-type dopants are segregated in the atomically flat metal/Si interfaces that help to reduce the effective Schott... View full abstract»

• ### A New Method to Extract Bulk Carrier Mobility in Germanium-on-Insulator

Publication Year: 2008, Page(s):1250 - 1254
Cited by:  Papers (6)
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A new method is presented to extract bulk carrier mobility of germanium-on-insulator (GeOI) films based on the data from the depletion mode of four-point probe pseudo-MOSFET measurement. Analytical models of the conductance in depletion region and related parameter extraction procedures are presented. This method is validated with both GeOI and silicon-on-insulator substrates prepared by layer tra... View full abstract»

• ### A Model With Temperature-Dependent Exponent for Hot-Carrier Injection in High-Voltage nMOSFETs Involving Hot-Hole Injection and Dispersion

Publication Year: 2008, Page(s):1255 - 1258
Cited by:  Papers (8)
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An improved hot-hole-involved interface-state generation model is proposed for hot-carrier injection (HCI) degradation in high-voltage (HV) nMOSFETs. This model is based on experiments over a wide range of temperatures, voltage conditions, simulation results, and the underlying physical mechanisms. The model provides a thorough picture of an HCI system in HV nMOSFETs, with hot-hole injection relat... View full abstract»

• ### Manufacturable Processes for $leq$ 32-nm-node CMOS Enhancement by Synchronous Optimization of Strain-Engineered Channel and External Parasitic Resistances

Publication Year: 2008, Page(s):1259 - 1264
Cited by:  Papers (29)
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Manufacturable processes to reduce both channel and external resistances (RExt) in CMOS devices are described. Simulations show that RExt will become equivalent to strained Si channel resistance near the 32-nm logic node. Tensile stress in plasma-enhanced chemical-vapor-deposited SiNx liners is increased with UV curing, boosting the NMOS drive current by 20% relati... View full abstract»

• ### A Parabolic Potential Barrier-Oriented Compact Model for the $k_{B}T$ Layer's Width in Nano-MOSFETs

Publication Year: 2008, Page(s):1265 - 1268
Cited by:  Papers (11)
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On the basis of a parabolic potential profile around the source-channel junction barrier of nanoscale MOSFETs, a new compact model is physically derived, which links the width of thermal energy kBT layer (a critical zone in the context of the backscattering theory) to the geometrical and bias parameters of the devices. The proposed model is supported by experimental data and by a critic... View full abstract»

## Aims & Scope

IEEE Transactions on Electron Devices publishes original and significant contributions relating to the theory, modeling, design, performance and reliability of electron and ion integrated circuit devices and interconnects.

Full Aims & Scope

## Meet Our Editors

Editor-in-Chief

Giovanni Ghione
Politecnico di Torino,
10129 Torino, Italy