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IEEE Journal of Solid-State Circuits

Issue 1 • Date Jan 1993

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Displaying Results 1 - 13 of 13
  • A CMOS logarithmic IF amplifier with unbalanced source-coupled pairs

    Publication Year: 1993, Page(s):78 - 83
    Cited by:  Papers (34)  |  Patents (7)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (388 KB)

    A CMOS logarithmic intermediate-frequency (IF) amplifier that is applied to mobile telecommunications equipment is presented. The CMOS logarithmic IF amplifier has pseudologarithmic rectifiers made from parallel-connecting full-wave rectifiers, consisting of unbalanced source-coupled pairs with the cross-coupled input stage and parallel-connected output stage. A ±3-dB logarithmic accuracy, ... View full abstract»

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  • A charge-based neural Hamming classifier

    Publication Year: 1993, Page(s):59 - 67
    Cited by:  Papers (25)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (776 KB)

    A charge-based fixed-weight neural Hamming classifier with an on-chip normalization facility is described. The classifier utilizes a purely capacitive synapse matrix for quantization and a multiport sense amplifier for discrimination. The discriminator is compatible with variable-weight synapses as well. A detailed analysis of the classifier configuration is presented; design issues are addressed,... View full abstract»

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  • Estimation of typical power of synchronous CMOS circuits using a hierarchy of simulators

    Publication Year: 1993, Page(s):26 - 39
    Cited by:  Papers (9)  |  Patents (1)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (1432 KB)

    Accurate power-dissipation analysis and correct supply net sizing are crucial aspects of the design of high-quality and low-cost integrated circuits. Information about the typical and maximal currents is required for both the chip and the system design. An accurate method for typical-current estimation is presented. It is based on circuit-level simulation over a number of clock cycles. Traditional... View full abstract»

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  • BiCMOS current cell and switch for digital-to-analog converters

    Publication Year: 1993, Page(s):68 - 71
    Cited by:  Papers (5)  |  Patents (3)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (284 KB)

    A BiCMOS current cell and current switch used in a current steering DAC are proposed. The BiCMOS self-calibrated current cell offers higher output resistance and smaller minimum voltage and shows up to a factor of 2 improvement in accuracy in simulations. The BiCMOS current switch has no base current error and achieves close to a factor of 2 improvement in simulated switching speed when compared t... View full abstract»

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  • A new compensation technique for resistive level shifters

    Publication Year: 1993, Page(s):93 - 95
    Cited by:  Papers (1)  |  Patents (2)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (196 KB)

    A compensation technique is introduced for resistive level-shifting stages that reduces the size of the compensating capacitor from 20-30 pF in conventional compensation to about 2-3 pF, making the stage more attractive for use in many analog ICs such as op amps, comparators, and wideband amplifiers View full abstract»

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  • A micropower-compatible time-multiplexed SC speech spectrum analyzer design

    Publication Year: 1993, Page(s):40 - 48
    Cited by:  Papers (14)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (764 KB)

    A micropower-compatible time-multiplexed switched-capacitor (SC) speech spectrum analyzer embodying several new design methodologies is described. In the bandpass filter (BPF) section, the DC offset differences between channels are reduced by a careful biquadratic filter design, and a capacitor sharing technique is employed to reduce chip area. A new time-multiplexed full-wave rectifier (FWR) is a... View full abstract»

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  • BiCMOS circuit technology for high-speed DRAMs

    Publication Year: 1993, Page(s):4 - 9
    Cited by:  Papers (6)  |  Patents (1)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (628 KB)

    A BiCMOS circuit technology featured by a novel bit-line sense amplifier has been developed. The bit-line sense amplifier is composed of a BiCMOS differential amplifier, the impedance-converting means featured by the CMOS current mirror circuit or the clocked CMOS inverter between the bit line and the base node of the BiCMOS differential amplifier, and a conventional CMOS flip-flop. This technolog... View full abstract»

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  • Analysis and design of a new race-free four-phase CMOS logic

    Publication Year: 1993, Page(s):18 - 25
    Cited by:  Papers (4)  |  Patents (3)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (668 KB)

    A four-phase dynamic logic, called the high-speed precharge-discharge CMOS (HS-PDCMOS) logic, is proposed and analyzed. Basically, the HS-PDCMOS logic uses two different units to implement the logic function and to drive the output load separately. Thus, a complex function can be implemented within a single gate and form the pipelined structure as well. The HS-PDCMOS logic needs four operation clo... View full abstract»

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  • Capacitive feedback technique for wide-band amplifiers

    Publication Year: 1993, Page(s):90 - 92
    Cited by:  Papers (25)  |  Patents (2)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (196 KB)

    A bandwidth-enhancing technique is presented for wideband amplifiers. In this technique a capacitive feedback scheme is used in analogy to resistive feedback amplifiers. As capacitive feedback does not lower gain, the technique does not trade off gain for bandwidth. Computer simulations and practical circuits show a considerable improvement over the conventional widebanding techniques View full abstract»

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  • A 2-ns detecting time, 2-μm CMOS built-in current sensing circuit

    Publication Year: 1993, Page(s):72 - 77
    Cited by:  Papers (43)  |  Patents (5)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (728 KB)

    Built-in current testing is known to enhance the defect coverage in CMOS VLSI. An experimental CMOS chip containing a high-speed built-in current sensing (BICS) circuit design is described. This chip has been fabricated through MOSIS 2-μm p-well CMOS technology. The power bus current of an 8×8 parallel multiplier is monitored. This BICS detects all implanted short-circuit defects and some... View full abstract»

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  • Trading speed for low power by choice of supply and threshold voltages

    Publication Year: 1993, Page(s):10 - 17
    Cited by:  Papers (137)  |  Patents (9)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (720 KB)

    The trading of speed for low power consumption in CMOS VLSI by using the supply voltage and the threshold voltage as variables was investigated. It is shown that it is desirable to minimize the supply voltage for minimizing the power consumption. The lower bound of the supply voltage and the possible decrease in power consumption without speed loss were investigated under different circuit constra... View full abstract»

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  • A programmable piecewise linear large-signal CMOS amplifier

    Publication Year: 1993, Page(s):84 - 89
    Cited by:  Papers (8)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (464 KB)

    A high-speed CMOS piecewise linear approximation circuit is presented that can be programmed for correction of nonlinearity after fabrication. The basic building block generates a linear segment, for which slope and position can be adjusted. Adjustments to adapt to arbitrary functions are done with floating gate devices fabricated in standard CMOS technology. The circuit is a voltage-to-current co... View full abstract»

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  • N-delta and differential average signal processors: detailing of their signal and noise response

    Publication Year: 1993, Page(s):49 - 58
    Cited by:  Papers (2)  |  Patents (2)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (616 KB)

    A detailed and complete derivation of the impulse response (and transfer function) for the most commonly used charge-coupled-device (CCD) output signal processing techniques is presented. A basic mathematical model is discussed for 2-δ double sampling and is then generalized to n-sample systems. The method is adapted to show how the impulse response for the differential averaging te... View full abstract»

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Aims & Scope

The IEEE Journal of Solid-State Circuits publishes papers each month in the broad area of solid-state circuits with particular emphasis on transistor-level design of integrated circuits.

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Editor-in-Chief
Michael Flynn
University of Michigan