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Computer-Aided Design of Integrated Circuits and Systems, IEEE Transactions on

Issue 5 • Date May 2008

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  • Table of contents

    Page(s): C1 - C4
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  • IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems publication information

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  • Unified Computation of Parameter Sensitivity and Signal-Injection Sensitivity in Nonlinear Oscillators

    Page(s): 781 - 790
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (383 KB) |  | HTML iconHTML  

    In this paper, two relevant computational aspects related to the design of nonlinear oscillators are considered: sensitivity to electrical parameter variation and sensitivity to small- amplitude injected signals. First, the analysis of the perturbation induced by parameter fluctuation is theoretically investigated, and a set of formal equations is deduced that allows us to correctly decompose amplitude and period variations. Second, the analysis of the perturbation induced by a generic weak signal is considered. This analysis is based on a well-consolidated approach that employs the Floquet eigenvector v1 (t) to project perturbation into the phase domain. It is shown that the same system of equations that formalizes the parameter-sensitivity problem can be exploited to calculate the v1 (t) projection vector. An efficient and reliable numerical implementation of a formal perturbation analysis is then proposed that allows the oscillator designer to evaluate both parameter sensitivity and signal-injection sensitivity in a homogeneous frame. View full abstract»

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  • Parasitic-Aware Optimization and Retargeting of Analog Layouts: A Symbolic-Template Approach

    Page(s): 791 - 802
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    Layout parasitics can significantly affect the performance of analog integrated circuits (ICs). In this paper, a systematic method of optimizing an existing analog layout considering parasitics is presented for technology migration and performance retargeting. This method represents the locations of layout rectangle edges as variables and extracts circuit and layout integrity such as device symmetry, matching, and design rules as constraints. To ensure the desired circuit performance, bounds of layout parasitics are determined first. These bounds are used to constrain the layout geometries while retargeting existing high-quality layouts across technologies and specification sets. The problem is then solved by a graph-based algorithm combined with nonlinear optimization. The proposed method has been implemented in a parasitic-aware automatic layout optimization and retargeting tool (intellectual property reuse-based analog IC layout). Its efficiency and effectiveness are demonstrated by successfully retargeting operational amplifiers within 1 min of CPU time. View full abstract»

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  • Modeling and Optimization for Soft-Error Reliability of Sequential Circuits

    Page(s): 803 - 816
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (880 KB) |  | HTML iconHTML  

    Due to reduction in device feature size and supply voltage, the sensitivity to radiation-induced transient faults of digital systems dramatically increases. In this paper, we present two approaches to evaluating the susceptibility of sequential circuits to soft errors. The first approach uses the Markov chain theory but can only provide steady-state behavior information. The second approach uses symbolic modeling based on binary decision diagrams/algebraic decision diagrams and circuit unrolling. The soft-error rate (SER) evaluation using this approach is demonstrated by the set of experimental results, which show that, for most of the benchmarks used, the SER decreases well below a given threshold (10-7 FIT) within ten clock cycles after the hit. The results obtained with the proposed symbolic framework are within 4% average error and up to 11 000x faster when compared to HSPICE detailed circuit simulation. The framework can be used for selective gate sizing targeting radiation hardening, leading up to 80% SER reduction when applied to a subset of ISCAS'89 benchmarks. View full abstract»

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  • Independent and Interdependent Latch Setup/Hold Time Characterization via Newton–Raphson Solution and Euler Curve Tracking of State-Transition Equations

    Page(s): 817 - 830
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    Characterizing setup/hold times of latches and registers, which is a task crucial for achieving timing closure of large digital designs, typically occupies months of computation in semiconductor industries. We present a novel approach to speed up latch characterization by formulating the setup/hold time problem as a scalar nonlinear equation ; this nonlinear algebraic formulation is derived from, and embeds within it, the state-transition function of the latch. We first present a technique to characterize setup and hold times independently of each other: by decoupling into two equations and and solving each equation using the Newton-Raphson method. Next, we also present a method for interdependent characterization of latch setup/hold times - a core component of techniques for pessimism reduction in timing analysis. We achieve this by solving the underdetermined nonlinear equation using a Moore-Penrose pseudoinverse-based Newton method. Furthermore, we use null-space information from the Newton's Jacobian matrix to efficiently find constant-clock-to- contours (in the setup/hold time plane) via an Euler-Newton curve-tracing procedure. We validate fast convergence and computational advantage for independent characterization on transmission gate and latch/register structures, obtaining speedups of , at high levels of accuracy, over the current standard of binary search. We validate the method for interdependent characterization on true single-phased clock and , obtaining speedups of more than 10 for tracing 17-24 points, over prior approaches while achieving superior accuracy; this speedup linearly increases with the precision with which curve tracing is desired. We also apply our method for interdependent characterization on a transmission gate register to illustrate limitations of our method. View full abstract»

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  • Quadratic Statistical MAX Approximation for Parametric Yield Estimation of Analog/RF Integrated Circuits

    Page(s): 831 - 843
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (665 KB) |  | HTML iconHTML  

    In this paper, we propose an efficient numerical algorithm for estimating the parametric yield of analog/RF circuits, considering large-scale process variations. Unlike many traditional approaches that assume normal performance distributions, the proposed approach is particularly developed to handle multiple correlated nonnormal performance distributions, thereby providing better accuracy than the traditional techniques. Starting from a set of quadratic performance models, the proposed parametric yield estimation conceptually maps multiple correlated performance constraints to a single auxiliary constraint by using a MAX operator. As such, the parametric yield is uniquely determined by the probability distribution of the auxiliary constraint and, therefore, can easily be computed. In addition, two novel numerical algorithms are derived from moment matching and statistical Taylor expansion, respectively, to facilitate efficient quadratic statistical MAX approximation. We prove that these two algorithms are mathematically equivalent if the performance distributions are normal. Our numerical examples demonstrate that the proposed algorithm provides an error reduction of 6.5 times compared to a normal-distribution-based method while achieving a runtime speedup of 10-20 times over the Monte Carlo analysis with 103 samples. View full abstract»

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  • Full-Chip Routing Considering Double-Via Insertion

    Page(s): 844 - 857
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    As the technology node advances into the nanometer era, via-open defects are one of the dominant failures due to the copper cladding process. To improve via yield and reliability, redundant-via insertion is a highly recommended technique proposed by foundries. Traditionally, double-via insertion is performed at the postlayout stage. The increasing design complexity, however, leaves very limited space for postlayout optimization. It is thus desirable to consider the double-via insertion at both the routing and postrouting stages. In this paper, we present a new full-chip gridless routing system considering double-via insertion for yield enhancement. To fully consider double vias, the router applies a novel two-pass, bottom-up routability-driven routing framework and features a new redundant-via aware detailed maze routing algorithm (which could be applied to both gridless and grid-based routing). We also propose a graph-matching based post-layout double-via insertion algorithm to achieve a higher insertion rate. In particular, the algorithm is optimal for grid-based routing with up to three routing layers and the stacked-via structure. Experiments show that our methods significantly improve the via count, number of dead vias, double-via insertion rates, and running times. View full abstract»

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  • Fixed-Outline Floorplanning: Block-Position Enumeration and a New Method for Calculating Area Costs

    Page(s): 858 - 871
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (801 KB) |  | HTML iconHTML  

    In this paper, we propose a fixed-outline floorplanning (FOFP) method [insertion-after-remove (IAR) FP]. An elaborated method for perturbing solutions, the IAR, is devised. This perturbation uses a technique of enumerating block positions, which is implemented based on the floorplan-representation sequence pair. The proposed perturbation method can greatly accelerate searching-based algorithms, such as simulated annealing, by skipping many solutions that fail to meet the fixed-outline constraint. Moreover, based on the analysis of the diverse objective functions used in the existing research works, we suggest for the FOFP a new objective function which is still effective when combined with other objectives. Experimental results show that, if area and wirelength are optimized simultaneously, using less time, the proposed method obtains much higher average success rate for the FOFP with various aspect ratios, while the wirelength with the fixed-outline constraint is reduced by 20% on average, compared with the latest fixed-outline floorplanners. On the other hand, we validated once more by experiments that an aspect ratio close to one is beneficial to wirelength, and hence, a larger area weight is necessary for the FOFP with a larger aspect ratio to ensure feasible solutions. View full abstract»

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  • Track Routing and Optimization for Yield

    Page(s): 872 - 882
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    In this paper, we propose track routing and optimization for yield (TROY), the first track router for the optimization of yield loss due to random defects. As the probability of failure (POF), which is an integral of the critical area and the defect size distribution, strongly depends on wire ordering, sizing, and spacing, track routing can play a key role in effective wire planning for yield optimization. However, a straightforward formulation of yield-driven track routing can be shown to be integer nonlinear programming, which is a nondeterministic polynomial-time complete problem. TROY overcomes the computational complexity by combining two effective techniques, i.e., the minimum Hamiltonian path (MHP) from graph theory and the second-order cone programming (SOCP) from mathematical optimization. First, TROY performs wire ordering to minimize the critical area for short defects by finding an MHP. Then, TROY carries out optimal wire sizing/spacing through SOCP optimization based on the given wire order. Since the SOCP can be optimally solved in near linear time, TROY efficiently achieves globally optimal wire sizing/spacing for the minimal POF. View full abstract»

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  • Simulation of Closely Related Dynamic Nonlinear Systems With Application to Process–Voltage–Temperature Corner Analysis

    Page(s): 883 - 892
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (860 KB) |  | HTML iconHTML  

    Even for a single circuit, it has become increasingly time consuming to simulate at the SPICE level. However, the situation is getting worse when it comes to simulating thousands of such circuits, where often one circuit is closely related to another. This problem arises in applications such as process-voltage-temperature corner circuit simulation or simulation-in-the-loop circuit optimization. The traditional approach to solving this problem is to repeatedly invoke SPICE simulation on each of those circuits. Such an approach does not exploit the similarity among those circuits and could lead to prohibitively high computational cost. This paper presents a new simulation approach capable of simulating hundreds and thousands of closely related systems with the computational cost comparable to or even less than that of a few simulations, yet with the same simulation accuracy and robustness. The proposed approach is based on the combination of the LU-factorization-based direct method (used to construct preconditioners) and Krylov-subspace-based iterative methods (used to solve circuit equations) to explore the common characteristics shared by a set of closely related systems. The key novelty is a systematic method that uses the fewest direct solving for underlying linearized systems and then solves the rest using Krylov-subspace-based iterative methods, with preconditioners computed from those LU factors. In addition, a method of automatically constructing preconditioners from device equations has been developed based on model compilation and demonstrated on MOS transistor Berkeley short-channel IGFET model (BSIM) models. Several circuit examples are included to show the effectiveness of the proposed approach. View full abstract»

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  • Process-Driven Variability Analysis of Single and Multiple Voltage–Frequency Island Latency-Constrained Systems

    Page(s): 893 - 905
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (832 KB) |  | HTML iconHTML  

    The problem of determining bounds for application completion times running on generic systems comprising single or multiple voltage-frequency islands (VFIs) with arbitrary topologies is addressed in the context of manufacturing-process-driven variability. The approach provides an exact solution for the system-level timing yield in synchronous single-voltage (SSV) and VFI systems with an underlying tree-based topology and a tight upper bound for generic non-tree-based topologies. The results show that: 1) timing yield for the overall source-to-sink completion time for generic systems can be modeled in an exact manner for both SSV and VFI systems and 2) multiple-VFI latency-constrained systems can achieve up to two times higher timing yield than their SSV counterparts. The results are formally proven and are supported by experimental results on two embedded applications, namely, a software-defined radio and a Moving Pictures Expert Group 2 encoder. View full abstract»

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  • Fault-Tolerant Distributed Deployment of Embedded Control Software

    Page(s): 906 - 919
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    Safety-critical feedback-control applications may suffer faults in the controlled plant as well as in the execution platform, i.e., the controller. Control theorists design the control laws to be robust with respect to the former kind of faults while assuming an idealized scenario for the latter. The execution platforms supporting modern real-time embedded systems, however, are distributed architectures made of heterogeneous components that may incur transient or permanent faults. Making the platform fault tolerant involves the introduction of design redundancy with obvious impact on the final cost. We present a design flow that enables the efficient exploration of redundancy/cost tradeoffs. After providing a system-level specification of the target platform and the fault model, designers can rely on the synthesis of the low-level fault-tolerance mechanisms. This is performed automatically as part of the embedded software deployment through the combination of the following three steps: replication, mapping, and scheduling. Our approach has a sound foundation in fault-tolerant data flow, a novel model of computation that simplifies the integration of formal validation techniques. Finally, we report on the application of our design flow to two case studies from the automotive industry: a steer-by-wire system from General Motors and a drive-by-wire system from BMW. View full abstract»

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  • Defect-Oriented Testing of RF Circuits

    Page(s): 920 - 931
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (532 KB) |  | HTML iconHTML  

    Radio-frequency (RF) test cost is soaring due to the increasing complexity of RF devices. Radically new test approaches that enable test time reduction while ensuring product quality are needed to reduce the overall product cost. In this paper, we present a test development methodology for RF circuits based on novel parametric, open-circuit, and short-circuit defect models. We inject parametric defects as deviations in physical circuit parameters, such as resistances, transistor widths, and lengths, and inject open- and short-circuit defects into the critical locations that are derived from the layout using inductive fault analysis. Despite fault injection, we consider a circuit unacceptable only if it violates any one of the performance specifications. Our test development method aims at reducing not only the number of measurements but also the overall test hardware cost by incorporating the relative setup cost of each measurement into our selection criteria. Experimental results on an RF front-end device show that our test methodology reduces the test time by 50% and the number of test setups by 17% while identifying all unacceptable circuit instances with a 99% failure coverage without any yield loss. View full abstract»

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  • Improving the Resolution of Single-Delay-Fault Diagnosis

    Page(s): 932 - 945
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    With feature sizes steadily shrinking, manufacturing defects and parameter variations often cause design-timing failures. It is essential that those errors be correctly and quickly diagnosed. The existing delay-fault diagnosis algorithms cannot identify delay faults that require nonrobust test patterns due to incorrect emulation of the failure analyzer's behavior. We propose a novel approach to performing delay-fault diagnosis for robust and nonrobust tests. We enhance the diagnostic resolution by utilizing passing patterns, processing failure logs at various slower frequencies, and applying n-detection and timing-aware automatic test pattern generation sets. Experimental results show that our approach can diagnose delay faults with good resolution. The algorithm is stable with respect to delay variations that manufactured chips might experience. View full abstract»

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  • On the Saturation of n -Detection Test Generation by Different Definitions With Increased n

    Page(s): 946 - 957
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    An n-detection test set contains different tests for each target fault. The value of is typically determined based on test set size constraints, and certain values have become standard. Appropriate values for are investigated in this paper by considering the saturation of the n-detection test generation process. As is increased, eventually, the rate of increase in test set quality starts dropping. Saturation occurs when the increase in test set quality with drops below a certain level. Three parameters of an n-detection test set are introduced to measure the saturation of the test generation process: 1) the fraction of faults detected times or less by the test set; 2) the fraction of faults detected fewer than times by the test set; and 3) the test set size relative to the size of a one-detection test set. It is demonstrated that the behavior of each one of these parameters follows a unique pattern as is increased, and certain features of this behavior can be used to identify saturation. All the parameters can be efficiently computed during the test generation process. View full abstract»

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  • FIR Filter Synthesis Considering Multiple Adder Graphs for a Coefficient

    Page(s): 958 - 962
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (442 KB) |  | HTML iconHTML  

    To reduce the hardware complexity of finite-impulse response (FIR) digital filters, this paper proposes a new filter synthesis algorithm. Considering multiple adder graphs for a coefficient, the proposed algorithm selects an adder graph that can be maximally sharable with the remaining coefficients, whereas previous dependence-graph algorithms consider only one adder graph when implementing a coefficient. In addition, an addition reordering technique is proposed to derive multiple adder graphs from a seed adder graph generated by using previous dependence-graph algorithms. Experimental results show that the proposed algorithm reduces the hardware cost of FIR filters by 22% and 3.4%, on average, compared to the Hartley and -dimensional reduced adder graph hybrid algorithms, respectively. View full abstract»

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  • Synthesis of Tile Sets for DNA Self-Assembly

    Page(s): 963 - 967
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (500 KB) |  | HTML iconHTML  

    This paper addresses the issues revolving around the synthesis of tile sets for DNA self-assembly as a promising approach for IC manufacturing in the nanoscale. As for a finite pattern, synthesis for minimizing tile or bond types is equivalent to a minimum graph coloring problem, two greedy algorithms that reduce the number of tiles (PATS_Tile) or bonds (PATS_Bond) in synthesized tile sets are proposed and evaluated. Both algorithms are O(l4) for a square pattern of dimension l. It is shown by simulation that PATS_Tile has a better average performance if both types of reduction must be accomplished. View full abstract»

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  • Accelerating Assertion Coverage With Adaptive Testbenches

    Page(s): 967 - 972
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    We present a new approach to bias random test generation for accelerating assertion coverage. The novelty of the proposed approach is that it treats the design under test as a black box and attempts to steer the simulation toward coverage points that are relevant for targeted assertions purely through external control. We present this approach over three different models with varying degrees of observability and control. The results demonstrate a significant speedup in assertion coverage as compared to randomized simulation. View full abstract»

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  • Cycle-Accurate Test Power Modeling and Its Application to SoC Test Architecture Design and Scheduling

    Page(s): 973 - 977
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    Concurrent testing of the cores in a core-based system- on-chip reduces the test application time but increases the test power consumption. Power models, test architecture design, and scheduling algorithms have been proposed to schedule the tests as concurrently as possible while respecting the power budget. The commonly used global peak power model, with a single value capturing the power dissipated by a core when tested, is simple for a scheduling algorithm to handle but is pessimistic. In this paper, we propose a cycle-accurate power model with a power value per clock cycle and a corresponding test architecture design and scheduling algorithm. The power model takes into account the switching activity in the scan chains caused by both the test stimuli and the expected test responses during scan-in, launch-and-capture, and scan-out. Furthermore, we allow a unique power model per wrapper-chain configuration as the activity in a core will be different depending on the number of wrapper chains at a core. Through circuit simulations on ISCAS'89 benchmarks, we demonstrate a high correlation between the real test power dissipation and our cycle-accurate test power model. Extensive experiments on ITC'02 benchmarks and an industrial design show that the testing time can be reduced substantially by using the proposed cycle-accurate test power model. View full abstract»

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  • A Synthesis Tool for CMOS RF Low-Noise Amplifiers

    Page(s): 977 - 982
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (536 KB) |  | HTML iconHTML  

    A stand-alone design automation tool tailored for radio frequency (RF) complementary metal-oxide-semiconductor (CMOS) low-noise amplifier (LNA) designs is presented. Rather than relying on commercially available circuit simulators such as Spectre or Hspice, the presented synthesis tool is self-contained with its own built-in modules for faster optimization. Foundry-provided silicon-verified RF device models are incorporated into the synthesis procedure for accurate parasitic modeling. The proposed synthesis tool can be used as an independent circuit design environment for LNAs or, alternatively, as an auxiliary tool generating an initial design for a commercial design environment to reduce design time. To validate the proposed approach, an LNA operating at 900 MHz is synthesized and fabricated in a 0.25-mum CMOS technology. Measurement results are presented, which shows the viability of the proposed synthesis tool. View full abstract»

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    Page(s): 983
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Aims & Scope

The purpose of this Transactions is to publish papers of interest to individuals in the areas of computer-aided design of integrated circuits and systems.

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Meet Our Editors

Editor-in-Chief

VIJAYKRISHNAN NARAYANAN
Pennsylvania State University
Dept. of Computer Science. and Engineering
354D IST Building
University Park, PA 16802, USA
vijay@cse.psu.edu