# IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems

## Filter Results

Displaying Results 1 - 24 of 24

Publication Year: 2008, Page(s):C1 - C4
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• ### IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems publication information

Publication Year: 2008, Page(s): C2
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• ### Unified Computation of Parameter Sensitivity and Signal-Injection Sensitivity in Nonlinear Oscillators

Publication Year: 2008, Page(s):781 - 790
Cited by:  Papers (19)
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In this paper, two relevant computational aspects related to the design of nonlinear oscillators are considered: sensitivity to electrical parameter variation and sensitivity to small- amplitude injected signals. First, the analysis of the perturbation induced by parameter fluctuation is theoretically investigated, and a set of formal equations is deduced that allows us to correctly decompose ampl... View full abstract»

• ### Parasitic-Aware Optimization and Retargeting of Analog Layouts: A Symbolic-Template Approach

Publication Year: 2008, Page(s):791 - 802
Cited by:  Papers (22)
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Layout parasitics can significantly affect the performance of analog integrated circuits (ICs). In this paper, a systematic method of optimizing an existing analog layout considering parasitics is presented for technology migration and performance retargeting. This method represents the locations of layout rectangle edges as variables and extracts circuit and layout integrity such as device symmet... View full abstract»

• ### Modeling and Optimization for Soft-Error Reliability of Sequential Circuits

Publication Year: 2008, Page(s):803 - 816
Cited by:  Papers (36)  |  Patents (1)
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Due to reduction in device feature size and supply voltage, the sensitivity to radiation-induced transient faults of digital systems dramatically increases. In this paper, we present two approaches to evaluating the susceptibility of sequential circuits to soft errors. The first approach uses the Markov chain theory but can only provide steady-state behavior information. The second approach uses s... View full abstract»

• ### Independent and Interdependent Latch Setup/Hold Time Characterization via Newton–Raphson Solution and Euler Curve Tracking of State-Transition Equations

Publication Year: 2008, Page(s):817 - 830
Cited by:  Papers (10)  |  Patents (3)
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Characterizing setup/hold times of latches and registers, which is a task crucial for achieving timing closure of large digital designs, typically occupies months of computation in semiconductor industries. We present a novel approach to speed up latch characterization by formulating the setup/hold time problem as a scalar nonlinear equation ; this nonlinear algebraic formulation is derived from, ... View full abstract»

• ### Quadratic Statistical $MAX$ Approximation for Parametric Yield Estimation of Analog/RF Integrated Circuits

Publication Year: 2008, Page(s):831 - 843
Cited by:  Papers (10)
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In this paper, we propose an efficient numerical algorithm for estimating the parametric yield of analog/RF circuits, considering large-scale process variations. Unlike many traditional approaches that assume normal performance distributions, the proposed approach is particularly developed to handle multiple correlated nonnormal performance distributions, thereby providing better accuracy than the... View full abstract»

• ### Full-Chip Routing Considering Double-Via Insertion

Publication Year: 2008, Page(s):844 - 857
Cited by:  Papers (36)  |  Patents (1)
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As the technology node advances into the nanometer era, via-open defects are one of the dominant failures due to the copper cladding process. To improve via yield and reliability, redundant-via insertion is a highly recommended technique proposed by foundries. Traditionally, double-via insertion is performed at the postlayout stage. The increasing design complexity, however, leaves very limited sp... View full abstract»

• ### Fixed-Outline Floorplanning: Block-Position Enumeration and a New Method for Calculating Area Costs

Publication Year: 2008, Page(s):858 - 871
Cited by:  Papers (33)
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In this paper, we propose a fixed-outline floorplanning (FOFP) method [insertion-after-remove (IAR) FP]. An elaborated method for perturbing solutions, the IAR, is devised. This perturbation uses a technique of enumerating block positions, which is implemented based on the floorplan-representation sequence pair. The proposed perturbation method can greatly accelerate searching-based algorithms, su... View full abstract»

• ### Track Routing and Optimization for Yield

Publication Year: 2008, Page(s):872 - 882
Cited by:  Papers (13)
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In this paper, we propose track routing and optimization for yield (TROY), the first track router for the optimization of yield loss due to random defects. As the probability of failure (POF), which is an integral of the critical area and the defect size distribution, strongly depends on wire ordering, sizing, and spacing, track routing can play a key role in effective wire planning for yield opti... View full abstract»

• ### Simulation of Closely Related Dynamic Nonlinear Systems With Application to Process–Voltage–Temperature Corner Analysis

Publication Year: 2008, Page(s):883 - 892
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Even for a single circuit, it has become increasingly time consuming to simulate at the SPICE level. However, the situation is getting worse when it comes to simulating thousands of such circuits, where often one circuit is closely related to another. This problem arises in applications such as process-voltage-temperature corner circuit simulation or simulation-in-the-loop circuit optimization. Th... View full abstract»

• ### Process-Driven Variability Analysis of Single and Multiple Voltage–Frequency Island Latency-Constrained Systems

Publication Year: 2008, Page(s):893 - 905
Cited by:  Papers (10)
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The problem of determining bounds for application completion times running on generic systems comprising single or multiple voltage-frequency islands (VFIs) with arbitrary topologies is addressed in the context of manufacturing-process-driven variability. The approach provides an exact solution for the system-level timing yield in synchronous single-voltage (SSV) and VFI systems with an underlying... View full abstract»

• ### Fault-Tolerant Distributed Deployment of Embedded Control Software

Publication Year: 2008, Page(s):906 - 919
Cited by:  Papers (13)
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Safety-critical feedback-control applications may suffer faults in the controlled plant as well as in the execution platform, i.e., the controller. Control theorists design the control laws to be robust with respect to the former kind of faults while assuming an idealized scenario for the latter. The execution platforms supporting modern real-time embedded systems, however, are distributed archite... View full abstract»

• ### Defect-Oriented Testing of RF Circuits

Publication Year: 2008, Page(s):920 - 931
Cited by:  Papers (14)
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Radio-frequency (RF) test cost is soaring due to the increasing complexity of RF devices. Radically new test approaches that enable test time reduction while ensuring product quality are needed to reduce the overall product cost. In this paper, we present a test development methodology for RF circuits based on novel parametric, open-circuit, and short-circuit defect models. We inject parametric de... View full abstract»

• ### Improving the Resolution of Single-Delay-Fault Diagnosis

Publication Year: 2008, Page(s):932 - 945
Cited by:  Papers (4)
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With feature sizes steadily shrinking, manufacturing defects and parameter variations often cause design-timing failures. It is essential that those errors be correctly and quickly diagnosed. The existing delay-fault diagnosis algorithms cannot identify delay faults that require nonrobust test patterns due to incorrect emulation of the failure analyzer's behavior. We propose a novel approach to pe... View full abstract»

• ### On the Saturation of $n$-Detection Test Generation by Different Definitions With Increased $n$

Publication Year: 2008, Page(s):946 - 957
Cited by:  Papers (1)
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An n-detection test set contains different tests for each target fault. The value of is typically determined based on test set size constraints, and certain values have become standard. Appropriate values for are investigated in this paper by considering the saturation of the n-detection test generation process. As is increased, eventually, the rate of increase in test set quality starts dropping.... View full abstract»

• ### FIR Filter Synthesis Considering Multiple Adder Graphs for a Coefficient

Publication Year: 2008, Page(s):958 - 962
Cited by:  Papers (5)
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To reduce the hardware complexity of finite-impulse response (FIR) digital filters, this paper proposes a new filter synthesis algorithm. Considering multiple adder graphs for a coefficient, the proposed algorithm selects an adder graph that can be maximally sharable with the remaining coefficients, whereas previous dependence-graph algorithms consider only one adder graph when implementing a coef... View full abstract»

• ### Synthesis of Tile Sets for DNA Self-Assembly

Publication Year: 2008, Page(s):963 - 967
Cited by:  Papers (20)
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This paper addresses the issues revolving around the synthesis of tile sets for DNA self-assembly as a promising approach for IC manufacturing in the nanoscale. As for a finite pattern, synthesis for minimizing tile or bond types is equivalent to a minimum graph coloring problem, two greedy algorithms that reduce the number of tiles (PATS_Tile) or bonds (PATS_Bond) in synthesized tile sets are pro... View full abstract»

• ### Accelerating Assertion Coverage With Adaptive Testbenches

Publication Year: 2008, Page(s):967 - 972
Cited by:  Papers (5)
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We present a new approach to bias random test generation for accelerating assertion coverage. The novelty of the proposed approach is that it treats the design under test as a black box and attempts to steer the simulation toward coverage points that are relevant for targeted assertions purely through external control. We present this approach over three different models with varying degrees of ob... View full abstract»

• ### Cycle-Accurate Test Power Modeling and Its Application to SoC Test Architecture Design and Scheduling

Publication Year: 2008, Page(s):973 - 977
Cited by:  Papers (17)  |  Patents (1)
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Concurrent testing of the cores in a core-based system- on-chip reduces the test application time but increases the test power consumption. Power models, test architecture design, and scheduling algorithms have been proposed to schedule the tests as concurrently as possible while respecting the power budget. The commonly used global peak power model, with a single value capturing the power dissipa... View full abstract»

• ### A Synthesis Tool for CMOS RF Low-Noise Amplifiers

Publication Year: 2008, Page(s):977 - 982
Cited by:  Papers (14)
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A stand-alone design automation tool tailored for radio frequency (RF) complementary metal-oxide-semiconductor (CMOS) low-noise amplifier (LNA) designs is presented. Rather than relying on commercially available circuit simulators such as Spectre or Hspice, the presented synthesis tool is self-contained with its own built-in modules for faster optimization. Foundry-provided silicon-verified RF dev... View full abstract»

• ### IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems Information for authors

Publication Year: 2008, Page(s): 983
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Publication Year: 2008, Page(s): 984
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• ### IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems society information

Publication Year: 2008, Page(s): C3
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## Aims & Scope

The purpose of this Transactions is to publish papers of interest to individuals in the area of computer-aided design of integrated circuits and systems composed of analog, digital, mixed-signal, optical, or microwave components.

Full Aims & Scope

## Meet Our Editors

Editor-in-Chief

VIJAYKRISHNAN NARAYANAN
Pennsylvania State University
Dept. of Computer Science. and Engineering
354D IST Building
University Park, PA 16802, USA
vijay@cse.psu.edu