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IEEE Transactions on Computers

Issue 3 • Date March 2008

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Displaying Results 1 - 14 of 14
  • [Front cover]

    Publication Year: 2008, Page(s): c1
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  • [Inside front cover]

    Publication Year: 2008, Page(s): c2
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  • Fast and Flexible Elliptic Curve Point Arithmetic over Prime Fields

    Publication Year: 2008, Page(s):289 - 302
    Cited by:  Papers (16)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (1900 KB) | HTML iconHTML Multimedia Media

    We present an innovative methodology for accelerating the elliptic curve point formulae over prime fields. This flexible technique uses the substitution of multiplication with squaring and other cheaper operations, by exploiting the fact that field squaring is generally less costly than multiplication. Applying this substitution to the traditional formulae, we obtain faster point operations in unp... View full abstract»

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  • Low-Transition Test Pattern Generation for BIST-Based Applications

    Publication Year: 2008, Page(s):303 - 315
    Cited by:  Papers (29)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (238 KB) | HTML iconHTML

    A low-transition test pattern generator, called the low-transition linear feedback shift register (LT-LFSR), is proposed to reduce the average and peak power of a circuit during test by reducing the transitions among patterns. Transitions are reduced in two dimensions: 1) between consecutive patterns (fed to a combinational only circuit) and 2) between consecutive bits (sent to a scan chain in a s... View full abstract»

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  • A Selective Trigger Scan Architecture for VLSI Testing

    Publication Year: 2008, Page(s):316 - 328
    Cited by:  Patents (1)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (538 KB) | HTML iconHTML

    Time, power, and data volume are among some of the most challenging issues for testing System-on-Chip (SoC) and have not been fully resolved even if a scan-based technique is employed. A novel architecture referred to the Selective Trigger Scan architecture, is introduced in this paper to address these issues. This architecture reduces switching activity in the circuitunder-test (CUT) and increase... View full abstract»

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  • An Energy-Delay Tunable Task Allocation Strategy for Collaborative Applications in Networked Embedded Systems

    Publication Year: 2008, Page(s):329 - 343
    Cited by:  Papers (30)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (549 KB) | HTML iconHTML

    Collaborative applications with energy and low-delay constraints are emerging in various networked embedded systems like wireless sensor networks and multimedia terminals. Conventional energy-aware task allocation schemes developed for collaborative applications only concentrated on energy-saving when making allocation decisions. Consequently, the length of the schedules generated by such allocati... View full abstract»

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  • Sharp Thresholds for Scheduling Recurring Tasks with Distance Constraints

    Publication Year: 2008, Page(s):344 - 358
    Cited by:  Papers (2)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (4542 KB) | HTML iconHTML

    The problem of identifying suitable conditions for the schedulability of (nonpreemptive) recurring tasks with deadlines is of great importance to real-time systems. In this paper, motivated by the problem of scheduling radar dwells, we show that scheduling problems of this nature show a sharp threshold behavior with respect to system utilization. Sharp thresholds are associated with phase transiti... View full abstract»

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  • eRAID: Conserving Energy in Conventional Disk-Based RAID System

    Publication Year: 2008, Page(s):359 - 374
    Cited by:  Papers (44)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (399 KB) | HTML iconHTML

    Recently, high-energy consumption has become a serious concern for both storage servers and data centers. Recent research studies have utilized the short transition times of multispeed disks to decrease energy consumption. Manufacturing challenges and costs have so far prevented commercial deployment of multispeed disks. In this paper, we propose an energy saving policy, eRAID (energy-efficient RA... View full abstract»

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  • An Efficient Data-Distribution Mechanism in a Processor-In-Memory (PIM) Architecture Applied to Motion Estimation

    Publication Year: 2008, Page(s):375 - 388
    Cited by:  Papers (2)  |  Patents (1)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (592 KB) | HTML iconHTML

    In general, the main purpose of using processor-in-memory (PIM) modules is to dramatically increase the data-level parallelism (DLP) and avoid the limited issue rate of current systems (even when they include SIMD extensions) caused by the limited data bandwidth and functional units. Our approach is to divide the PIM module into hundreds of smaller pieces so that each of these smaller PIMs can exe... View full abstract»

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  • An Instruction Throughput Model of Superscalar Processors

    Publication Year: 2008, Page(s):389 - 403
    Cited by:  Papers (15)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (491 KB) | HTML iconHTML

    Advances in semiconductor technology enable larger processor design spaces, leading to increasingly complex systems. At an initial stage, designers must evaluate many architecture design points to achieve a suitable design. Currently, most architecture exploration is performed using cycle accurate simulators. Although accurate, these tools are slow, thus limiting a comprehensive design search. The... View full abstract»

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  • A Low-Latency Pipelined 2D and 3D CORDIC Processors

    Publication Year: 2008, Page(s):404 - 417
    Cited by:  Papers (9)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (329 KB) | HTML iconHTML

    The unfolded and pipelined CORDIC is a high-performance hardware element that produces a wide variety of one and two argument functions with high throughput. The reduction in delay, power, and area (cost) are of significant interest regarding this module due to its high demand for resources. The linear approximation to rotation has been proposed to achieve such reductions. However, the schemes for... View full abstract»

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  • Interval-Based Timing Constraints Their Satisfactions and Applications

    Publication Year: 2008, Page(s):418 - 432
    Cited by:  Papers (1)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (1237 KB) | HTML iconHTML

    In real systems, an error range (±Δ) is often given to a time stamp (t) for an observed event. Such practice implicitly states that the event happens anytime in the interval [t-Δ1, t+Δ2]. Hence, constraints based on intervals are more realistic. However, when a constraint is extended from a point to an interval, its satisfaction is not a simple Boolean value; instead, a ... View full abstract»

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  • TC Information for authors

    Publication Year: 2008, Page(s): c3
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  • [Back cover]

    Publication Year: 2008, Page(s): c4
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Aims & Scope

The IEEE Transactions on Computers is a monthly publication with a wide distribution to researchers, developers, technical managers, and educators in the computer field.

Full Aims & Scope

Meet Our Editors

Editor-in-Chief
Paolo Montuschi
Politecnico di Torino
Dipartimento di Automatica e Informatica
Corso Duca degli Abruzzi 24 
10129 Torino - Italy
e-mail: pmo@computer.org