IEEE Design & Test of Computers

Issue 2 • March-April 2008

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Displaying Results 1 - 25 of 29
  • [Front cover]

    Publication Year: 2008, Page(s): c1
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  • IEEE Computer Society Digital Library [advertisement]

    Publication Year: 2008, Page(s): c2
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  • Test compression saves bits, cycles, and money

    Publication Year: 2008, Page(s): 105
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  • Table of contents

    Publication Year: 2008, Page(s):106 - 107
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  • IEEE Computer Society Membership application

    Publication Year: 2008, Page(s):108 - 110
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  • [Masthead]

    Publication Year: 2008, Page(s): 111
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  • Guest Editors' Introduction: Progress in Test Compression

    Publication Year: 2008, Page(s):112 - 113
    Cited by:  Papers (1)
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  • Historical Perspective on Scan Compression

    Publication Year: 2008, Page(s):114 - 120
    Cited by:  Papers (25)  |  Patents (2)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (482 KB) | HTML iconHTML

    The beginnings of the modern-day IC test trace back to the introduction of such fundamental concepts as scan, stuck-at faults, and the D-algorithm. Since then, several subsequent technologies have made significant improvements to the state of the art. Today, IC test has evolved into a multifaceted industry that supports innovation. Scan compression technology has proven to be a powerful antidote t... View full abstract»

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  • Advertiser/Product Index

    Publication Year: 2008, Page(s): 121
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  • VirtualScan: Test Compression Technology Using Combinational Logic and One-Pass ATPG

    Publication Year: 2008, Page(s):122 - 130
    Cited by:  Papers (24)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (568 KB) | HTML iconHTML

    IC testing based on a full-scan design methodology and ATPG is the most widely used test strategy today. However, rapidly growing test costs are severely challenging the applicability of scan-based testing. Both test data size and number of test cycles increase drastically as circuit size grows and feature size shrinks. For a full-scan circuit, test data volume and test cycle count are both propor... View full abstract»

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  • IEEE Computer Society Information

    Publication Year: 2008, Page(s): 131
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  • UMC-Scan Test Methodology: Exploiting the Maximum Freedom of Multicasting

    Publication Year: 2008, Page(s):132 - 140
    Cited by:  Papers (21)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (599 KB) | HTML iconHTML

    Industry has used scan-based designs widely to promote test quality. However, for larger designs, the growing test data volume has significantly increased test cost because of excessively long test times and elevated tester memory and external test channel requirements. To address these problems, researchers have proposed numerous test compression architectures. In this article, we propose a flexi... View full abstract»

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  • Distributed Systems Online [advertisement]

    Publication Year: 2008, Page(s): 141
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  • Hierarchical Test Compression for SoC Designs

    Publication Year: 2008, Page(s):142 - 148
    Cited by:  Papers (7)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (1127 KB) | HTML iconHTML

    Capitalizing on the larger capacity of today's ICs, designers are using yesterday's chips as modules in today's chips. DFT methodologies, which usually work on a large, flat design, must begin to take this reuse into account. This article shows how to use the X-compact compression technique in a hierarchical environment. View full abstract»

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  • IEEE Pervasive Computing Subscription Information

    Publication Year: 2008, Page(s): 149
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  • Loopback DFT for Low-Cost Test of Single-VCO-Based Wireless Transceivers

    Publication Year: 2008, Page(s):150 - 159
    Cited by:  Papers (5)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (1579 KB) | HTML iconHTML

    This article discusses a loopback DFT test approach for RFIC chips that provides quick, economical test results at the wafer level. By performing RF testing before chip packaging, the authors reduce test cost. They show that test yield on the ATE for Texas Instruments' RFIC devices is high when this loopback DFT approach is used. View full abstract»

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  • Wireless System for Microwave Test Signal Generation

    Publication Year: 2008, Page(s):160 - 166
    Cited by:  Papers (2)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (690 KB) | HTML iconHTML

    RF testing involves distribution of an RF source to chips. This article describes an RF embedded-testing technique that distributes RF sources to the unpackaged RF chip via an antenna. The authors demonstrate this technique on a 5-GHz low-noise amplifier, thus eliminating expensive RF probes and test fixtures. View full abstract»

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  • Software 2008 Editorial Calendar

    Publication Year: 2008, Page(s): 167
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  • An Illustrated Methodology for Analysis of Error Tolerance

    Publication Year: 2008, Page(s):168 - 177
    Cited by:  Papers (22)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (737 KB) | HTML iconHTML

    Noise, defects, and process variations are likely to cause very unpredictable circuit performance in future billion-transistor dies, hence decreasing raw yield. Error tolerance is one of several techniques that can increase effective yield. This article presents a methodology for analyzing the suitability of error tolerance for a particular application and implementation. The methodology, illustra... View full abstract»

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  • Device Model for Ballistic CNFETs Using the First Conducting Band

    Publication Year: 2008, Page(s):178 - 186
    Cited by:  Papers (36)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (779 KB) | HTML iconHTML

    This efficient approximation model for the drain-source current in a CNFET is analytic, its execution is fast, and it is suitable for simulating circuits consisting of many CNFET devices in a CAD environment. Evaluation results show that the model encounters a very modest normalized RMS error for diameter, Fermi level, and bias variations, while significantly improving simulation performance. View full abstract»

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  • DATC Newsletter

    Publication Year: 2008, Page(s): 187
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  • Discussing DRAM and CMOS Scaling with Inventor Bob Dennard

    Publication Year: 2008, Page(s):188 - 191
    Cited by:  Papers (1)
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  • Standards update from IP 07

    Publication Year: 2008, Page(s):192 - 193
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (240 KB) | HTML iconHTML

    Compared to other areas of electronics design, the IP industry has lagged in the development of comprehensive standards for description, integration, verification, and evaluation. This lag has stifled the development of automation tools, which have been so effective in growing other aspects of the electronics design industry. The current state of IP standards is a major roadblock to industry growt... View full abstract»

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  • Building your yield of dreams [review of Design for Manufacturability and Yield for Nano-Scale CMOS by Charles Chiang and Jamil Kawa; 2007]

    Publication Year: 2008, Page(s):194 - 195
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  • CEDA Currents

    Publication Year: 2008, Page(s):196 - 197
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Aims & Scope

This Periodical ceased production in 2012. The current retitled publication is IEEE Design & Test.

Full Aims & Scope

Meet Our Editors

Editor-in-Chief
Krishnendu Chakrabarty