# IEEE Transactions on Electron Devices

## Filter Results

Displaying Results 1 - 25 of 30

Publication Year: 2008, Page(s):C1 - C4
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• ### IEEE Transactions on Electron Devices publication information

Publication Year: 2008, Page(s): C2
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• ### Theoretical Study of Electron Confinement in Submicrometer GaN HFETs Using a Thermally Self-Consistent Monte Carlo Method

Publication Year: 2008, Page(s):945 - 953
Cited by:  Papers (16)
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This paper studies various existing advanced GaN heterostructures, which are introduced to provide better confinement of the 2-D electron gas in the channel using a Monte Carlo simulation method coupled with a 3-D solution of the heat diffusion equation. It is shown that the introduction of acceptors in the buffer layer and the introduction of an InGaN back-barrier layer at the bottom of the chann... View full abstract»

• ### Gallium–Indium–Zinc-Oxide-Based Thin-Film Transistors: Influence of the Source/Drain Material

Publication Year: 2008, Page(s):954 - 960
Cited by:  Papers (133)  |  Patents (1)
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During the last years, oxide semiconductors have shown that they will have a key role in the future of electronics. In fact, several research groups have already presented working devices with remarkable electrical and optical properties based on these materials, mainly thin-film transistors (TFTs). Most of these TFTs use indium-tin oxide (ITO) as the material for source/drain electrodes. This pap... View full abstract»

• ### Nitrogen Implantation to Improve Electron Channel Mobility in 4H-SiC MOSFET

Publication Year: 2008, Page(s):961 - 967
Cited by:  Papers (20)  |  Patents (1)
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Normally off 4H-SiC MOSFET devices have been fabricated on a p-type semiconductor and electrically characterized at different temperatures. A gate oxide obtained by nitrogen ion implantation performed before the thermal oxidation of SiC has been implemented in n-channel MOSFET technology. Two samples with a nitrogen concentration at the SiO2/SiC interface of 5 X 1018 and 1.5 ... View full abstract»

• ### An Augmented Small-Signal HBT Model With Its Analytical Based Parameter Extraction Technique

Publication Year: 2008, Page(s):968 - 972
Cited by:  Papers (9)
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This paper presents a simple and systematic extraction technique for an augmented heterojunction bipolar transistor (HBT) small-signal model with improved representation for the intrinsic base and external base-collector junction. The extraction results for a 1 times 10 mum2 HBT allow the investigation of the validity of the usual representation of ac emitter current crowding, as a capa... View full abstract»

• ### Contact Resistance in Nanocrystalline Silicon Thin-Film Transistors

Publication Year: 2008, Page(s):973 - 977
Cited by:  Papers (8)
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Thin-film transistors (TFTs) of nanocrystalline silicon (nc-Si:H) made by plasma-enhanced chemical vapor deposition have higher electron and hole field-effect mobilities than their amorphous counterparts. However, as the intrinsic carrier mobilities are raised, the effective carrier mobilities easily can become limited by the source/drain contact resistance. To evaluate the contact resistance, the... View full abstract»

• ### Optoelectronic Characteristics of Direct-Current and Alternating-Current White Thin-Film Light-Emitting Diodes Based on Hydrogenated Amorphous Silicon Nitride Film

Publication Year: 2008, Page(s):978 - 985
Cited by:  Papers (8)
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Direct-current and alternating-current white thin- film light-emitting diodes (DCW and ACW TFLEDs) have been fabricated and demonstrated with the intrinsic hydrogenated amorphous silicon nitride (i-a-SiN:H) film as the luminescent layer. The achievable brightness of the representative DCW and ACW TFLEDs were 200 and 170 cd/m2 at an injection-current density of 600 and 100 mA/cm2 View full abstract»

• ### A MOS Image Sensor With a Digital-Microlens

Publication Year: 2008, Page(s):986 - 991
Cited by:  Papers (6)  |  Patents (6)
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We have developed a MOS image sensor with digital-microlenses (DMLs), each of which has an effective refractive index realized by variation of the subwavelength separations between the concentric SiO2 ring walls. The effective refractive index profiles are optimized for the location of each pixel. The light-collection efficiency of the image sensor is twice as high as that of a conventi... View full abstract»

• ### The Operation Characteristics of an Alternating Current Plasma Display Panel With Si-Doped MgO Protecting Layer

Publication Year: 2008, Page(s):992 - 996
Cited by:  Papers (7)
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In this paper, the operation characteristics of an ac plasma display panel (PDP) with Si-doped MgO protecting layer are investigated. The test panels are fabricated with the protecting layers of conventional MgO and Si-doped MgO, and the operation voltage margin, luminous efficacy, and address discharge time lag are observed. Even though the test panel with Si-doped MgO protecting layer showed low... View full abstract»

• ### Gate Oxide Wear-Out and Breakdown Effects on the Performance of Analog and Digital Circuits

Publication Year: 2008, Page(s):997 - 1004
Cited by:  Papers (28)  |  Patents (1)
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To investigate the impact of gate oxide degradation and breakdown (BD) on complimentary metal-oxide-semiconductor circuit functionality, an accurate description of the electrical characteristics of the stressed devices, which can be included in circuit simulators, is needed. In this paper, a description of the stressed device performance that considers, on the one hand, the variation of the channe... View full abstract»

• ### Modeling and Analysis of the Asymmetric Source/Drain Extension CMOS Transistors for Nanoscale Technologies

Publication Year: 2008, Page(s):1005 - 1012
Cited by:  Papers (7)  |  Patents (1)
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The asymmetric source/drain extension (ASDE) transistor can be a suitable option because of improved short channel effects in technology nodes beyond 32 nm. In this paper, we have analyzed the impact of asymmetric drain extension reduction on the device metrics, namely, gate-to-drain capacitance, drain current, subthreshold leakage, and gate tunneling leakage current. Also, analytical models have ... View full abstract»

• ### The Tunnel Source (PNPN) n-MOSFET: A Novel High Performance Transistor

Publication Year: 2008, Page(s):1013 - 1019
Cited by:  Papers (150)  |  Patents (1)
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As MOSFET is scaled below 90 nm, many daunting challenges arise. Short-channel effects (SCEs; drain-induced barrier lowering and VTHmiddotrolloff), off-state leakage, parasitic capacitance, and resistance severely limit the performance of these transistors. New device innovations are essential to overcome these difficulties. In this paper, we propose the concept of a novel tunnel source... View full abstract»

• ### Modeling of $V_{rm th}$ Shift in nand Flash-Memory Cell Device Considering Crosstalk and Short-Channel Effects

Publication Year: 2008, Page(s):1020 - 1026
Cited by:  Papers (27)  |  Patents (2)
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A threshold-voltage (Vth) shift of sub-100-nm NAND flash-memory cell transistors was modeled systematically, and the modeling was verified by comparing with the data from measurement and 3-D device simulation. The Vth shift of the NAND flash-memory cell was investigated by changing parameters such as gate length, width, drain voltage, dielectric material between cells, space ... View full abstract»

• ### Electrical Properties of Low-Temperature-Compatible P-Channel Polycrystalline-Silicon TFTs Using High-$kappa$ Gate Dielectrics

Publication Year: 2008, Page(s):1027 - 1034
Cited by:  Papers (8)
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In this paper, we describe a systematic study of the electrical properties of low-temperature-compatible p-channel polycrystalline-silicon thin-film transistors (poly-Si TFTs) using HfO2 and HfSiOx, high-k gate dielectrics. Because of their larger gate capacitance density, the TFTs containing the high-k gate dielectrics exhibited superior device performance in terms of higher... View full abstract»

• ### A New Method to Determine Effective Lateral Doping Abruptness and Spreading-Resistance Components in Nanoscale MOSFETs

Publication Year: 2008, Page(s):1035 - 1041
Cited by:  Papers (4)
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A comprehensive technique for the accurate extraction of the effective lateral doping abruptness and the spreading-resistance components in source/drain extension (EXT) regions is presented by FET on-resistance characterization and physical resistance modeling. The spreading-resistance components under EXT-to-gate overlap, and spacer regions are successfully correlated to the lateral EXT doping ab... View full abstract»

• ### Ultralow-Thermal-Budget CMOS Process Using Flash-Lamp Annealing for 45 nm Metal/High- $k$ FETs

Publication Year: 2008, Page(s):1042 - 1049
Cited by:  Papers (10)  |  Patents (1)
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This paper describes a fabrication process that uses flash-lamp annealing (FLA) and the characteristics of the CMOS transistors that are constructed with an ultralow-thermal- budget process tuned for 45-nm metal/high-k FETs. FLA enhances the drivability of pFETs with the solid-phase epitaxial (SPE) extension junction, but reducing the thermal budget deteriorates the poly-gate depletion and the ele... View full abstract»

• ### Nonuniform Mobility-Enhancement Techniques and Their Impact on Device Performance

Publication Year: 2008, Page(s):1050 - 1057
Cited by:  Papers (15)
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Nowadays, process-induced stress is the preferential industrial method to enhance circuit performances. One of the most popular techniques is the strain induced by contact etch-stop layer. This technology induces a drain-current enhancement which depends on the device dimensions. This strong behavior has already been reported in the literature. In this paper, we propose a simple semianalytical phy... View full abstract»

• ### Modeling and Layout Optimization of Differential Inductors for Silicon-Based RFIC Applications

Publication Year: 2008, Page(s):1058 - 1066
Cited by:  Papers (6)
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A scalable RF differential inductor model has been developed, enabling device performance versus layout size tradeoffs and optimization as well as accurate circuit predictions. Comparing inductors with identical inductance values up to an operating frequency of 10 GHz, large conductor width designs are found to yield good performance for inductors with small inductance values. As differential indu... View full abstract»

• ### Nonuniform RF Overstress in High-Power Transistors and Amplifiers

Publication Year: 2008, Page(s):1067 - 1073
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Nonuniform light emission from power transistors at 2-3-dB compression levels has been imaged using a microscope- mounted camera. The nonuniformity depends on the device lateral geometry, load impedance, dc and radio frequency (RF) conditions, and the negative gate current, which is a result of the RF-induced impact ionization in the transistors. Numerical simulations demonstrated a nonuniform dis... View full abstract»

• ### Matching the Transconductance Characteristics of CMOS ISFET Arrays by Removing Trapped Charge

Publication Year: 2008, Page(s):1074 - 1079
Cited by:  Papers (39)  |  Patents (94)
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This paper presents an approach for matching the transconductance characteristics of CMOS ISFET arrays by removing trapped charge. We describe how to design arrays of floating-gate ISFETs so that ultraviolet (UV) radiation and bulk-substrate biasing can be used to remove the random amount of trapped charge that accumulates on the gates during fabrication. The approach is applied directly to a prot... View full abstract»

• ### Analytical Model of Amorphous Layer Thickness Formed by High-Tilt-Angle As Ion Implantation

Publication Year: 2008, Page(s):1080 - 1084
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We previously proposed a compact model of amorphous layer thickness over a wide range of ion implantation conditions using a vertical ion implantation profile parameter database. We also proposed a new parameter for the through dose. We extended the model to any tilt angle for ion implantation using one more parameter for the lateral straggling of the ion implantation profile. View full abstract»

• ### Strained CMOS Devices With Shallow-Trench-Isolation Stress Buffer Layers

Publication Year: 2008, Page(s):1085 - 1089
Cited by:  Papers (21)  |  Patents (1)
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In this brief, shallow-trench-isolation (STI) stress buffer techniques, including sidewall stress buffer and channel surface buffer layers, are developed to reduce the impact of compressive STI stress on the mobility of advanced n-type MOS (NMOS) devices. Our investigation shows that a 7% driving current gain at an NMOS device has been achieved, whereas no degradation at a p-type MOS (PMOS) device... View full abstract»

• ### Micro-Raman/Infrared Temperature Monitoring of Gunn Diodes

Publication Year: 2008, Page(s):1090 - 1093
Cited by:  Papers (6)
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Temperature measurements have been made on Gunn diode samples, using both infrared (IR) and micro-Raman spectroscopy. Micro-Raman spectroscopy was used to give high-resolution temperature measurements on the active transit region of the Gunn diode. These were directly compared with IR thermal measurements made across the mesa region and also on the metallized top contact of the diode. View full abstract»

• ### Corrections to “a three-dimensional simulation study of the performance of carbon nanotube field-effect transistors with doped reservoirs and realistic geometry” [Aug 06 1782-1788]

Publication Year: 2008, Page(s):1094 - 1095
Cited by:  Papers (4)
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In the above titled paper (ibid., vol. 53, no. 8, pp. 1782-1788, Aug 06), there are some errors in the results. This errata corrects Figs. 5-11, and 13 of the original paper and adds Fig. 14. View full abstract»

## Aims & Scope

IEEE Transactions on Electron Devices publishes original and significant contributions relating to the theory, modeling, design, performance and reliability of electron and ion integrated circuit devices and interconnects.

Full Aims & Scope

## Meet Our Editors

Editor-in-Chief

Giovanni Ghione
Politecnico di Torino,
10129 Torino, Italy