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Electron Devices, IEEE Transactions on

Issue 4 • Date April 2008

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  • Table of contents

    Publication Year: 2008 , Page(s): C1 - C4
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  • IEEE Transactions on Electron Devices publication information

    Publication Year: 2008 , Page(s): C2
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  • Theoretical Study of Electron Confinement in Submicrometer GaN HFETs Using a Thermally Self-Consistent Monte Carlo Method

    Publication Year: 2008 , Page(s): 945 - 953
    Cited by:  Papers (8)
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (428 KB) |  | HTML iconHTML  

    This paper studies various existing advanced GaN heterostructures, which are introduced to provide better confinement of the 2-D electron gas in the channel using a Monte Carlo simulation method coupled with a 3-D solution of the heat diffusion equation. It is shown that the introduction of acceptors in the buffer layer and the introduction of an InGaN back-barrier layer at the bottom of the channel, in a single heterojunction AlGaN/GaN heterostructure field-effect transistor (HFET), improve charge confinement in the channel. It is also shown how the inclusion of an AlGaN carrier exclusion layer at the AlGaN/GaN interface significantly improves the current-handling capability of the HFET. This paper is also a study of the effect of carrier confinement on the thermal performance of each structure; the results show that better confinement of carriers in the HFET channel is accompanied by an enhancement of the influence of self-heating effects. View full abstract»

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  • Gallium–Indium–Zinc-Oxide-Based Thin-Film Transistors: Influence of the Source/Drain Material

    Publication Year: 2008 , Page(s): 954 - 960
    Cited by:  Papers (66)
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (638 KB) |  | HTML iconHTML  

    During the last years, oxide semiconductors have shown that they will have a key role in the future of electronics. In fact, several research groups have already presented working devices with remarkable electrical and optical properties based on these materials, mainly thin-film transistors (TFTs). Most of these TFTs use indium-tin oxide (ITO) as the material for source/drain electrodes. This paper focuses on the investigation of different materials to replace ITO in inverted-staggered TFTs based on gallium-indium-zinc oxide (GIZO) semiconductor. The analyzed electrode materials were indium-zinc oxide, Ti, Al, Mo, and Ti/Au, with each of these materials used in two different kinds of devices: one was annealed after GIZO channel deposition but prior to source/drain deposition, and the other was annealed at the end of device production. The results show an improvement on the electrical properties when the annealing is performed at the end (for instance, with Ti/Au electrodes, mobility rises from 19 to 25 cm2/V ldr s, and turn-on voltage drops from 4 to 2 V). Using time-of-flight secondary ion mass spectrometry (TOF-SIMS), we could confirm that some diffusion exists in the source/drain electrodes/semiconductor interface, which is in close agreement with the obtained electrical properties. In addition to TOF-SIMS results for relevant elements, electrical characterization is presented for each kind of device, including the extraction of source/drain series resistances and TFT intrinsic parameters, such as (intrinsic mobility) and VTi (intrinsic threshold voltage). View full abstract»

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  • Nitrogen Implantation to Improve Electron Channel Mobility in 4H-SiC MOSFET

    Publication Year: 2008 , Page(s): 961 - 967
    Cited by:  Papers (12)
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (275 KB) |  | HTML iconHTML  

    Normally off 4H-SiC MOSFET devices have been fabricated on a p-type semiconductor and electrically characterized at different temperatures. A gate oxide obtained by nitrogen ion implantation performed before the thermal oxidation of SiC has been implemented in n-channel MOSFET technology. Two samples with a nitrogen concentration at the SiO2/SiC interface of 5 X 1018 and 1.5 X 1019 cm-3 and one unimplanted sample have been manufactured. The sample with the highest N concentration at the interface presents the highest channel mobility and the lowest threshold voltage. For increasing temperature, in all the samples, the threshold voltage decreases, and the electron channel mobility increases. The latter case attains a maximum value of about 40 cm2/V ldr s at 200degC for the sample with the highest N concentration. These trends are explained by the reduction of interface electron traps in the upper half of the band gap toward the conduction band edge. These results demonstrate that N implantation can be effectively used to improve the electrical performances of an n-type surface channel 4H-SiC MOSFET. View full abstract»

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  • An Augmented Small-Signal HBT Model With Its Analytical Based Parameter Extraction Technique

    Publication Year: 2008 , Page(s): 968 - 972
    Cited by:  Papers (3)
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (356 KB) |  | HTML iconHTML  

    This paper presents a simple and systematic extraction technique for an augmented heterojunction bipolar transistor (HBT) small-signal model with improved representation for the intrinsic base and external base-collector junction. The extraction results for a 1 times 10 mum2 HBT allow the investigation of the validity of the usual representation of ac emitter current crowding, as a capacitance in shunt with the spreading resistance. View full abstract»

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  • Contact Resistance in Nanocrystalline Silicon Thin-Film Transistors

    Publication Year: 2008 , Page(s): 973 - 977
    Cited by:  Papers (1)
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (638 KB) |  | HTML iconHTML  

    Thin-film transistors (TFTs) of nanocrystalline silicon (nc-Si:H) made by plasma-enhanced chemical vapor deposition have higher electron and hole field-effect mobilities than their amorphous counterparts. However, as the intrinsic carrier mobilities are raised, the effective carrier mobilities easily can become limited by the source/drain contact resistance. To evaluate the contact resistance, the nc-Si:H TFTs are made with a range of channel lengths. The TFTs are fabricated in a staggered top-gate bottom source/drain geometry. Both the intrinsic and the - or -doped nc-Si:H source/drain layers are deposited at 80-MHz excitation frequency at a substrate temperature of 150 . Transmission electron microscopy of the TFT cross section indicates that crystallites of doped nc-Si:H nucleate on top of the Cr source/drain contacts. As the film thickness increases, the crystallites coalesce, and the leaf-shaped crystal grains extend through the doped layer to the channel i layer. The contact resistance is estimated by measuring IDS for several channel lengths at fixed gate and drain voltages. The results show that the contact resistance depends on the gate voltage and that the source/drain current of these TFTs at VDS = 10 V becomes limited by the contact resistance when the channel length is less than 10 mum for n-channel and less than 25 mum for p-channel. View full abstract»

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  • Optoelectronic Characteristics of Direct-Current and Alternating-Current White Thin-Film Light-Emitting Diodes Based on Hydrogenated Amorphous Silicon Nitride Film

    Publication Year: 2008 , Page(s): 978 - 985
    Cited by:  Papers (5)
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (445 KB) |  | HTML iconHTML  

    Direct-current and alternating-current white thin- film light-emitting diodes (DCW and ACW TFLEDs) have been fabricated and demonstrated with the intrinsic hydrogenated amorphous silicon nitride (i-a-SiN:H) film as the luminescent layer. The achievable brightness of the representative DCW and ACW TFLEDs were 200 and 170 cd/m2 at an injection-current density of 600 and 100 mA/cm2, respectively. The electroluminescence (EL) threshold voltage of the DCW TFLED was 10.9 V, and its peak wavelength and full-width at half-maximum (FWHM) of the EL spectrum were about 455 and 230 nm, respectively. For the ACW TFLED, the EL threshold voltage was 8.4 V, and its peak wavelength and FWHM of the EL spectrum were about 535 and 260 nm, respectively. In addition, their current-conduction mechanism was also investigated. Within the lower applied-voltage region, they showed an ohmic current, while for the higher applied-voltage region, the Frenkel-Poole emission was the main mechanism. It was also found that the H2 -plasma treatment of luminescent i-a-SiN:H layer of an ACW TFLED played an important role in improving device performances, such as decreased EL threshold voltage, increased brightness, and broadened and blue-shifted EL spectrum. The EL spectra of an ACW TFLED under either DC forward or reverse bias or the sinusoidal AC voltage were qualitatively very similar, with a peak wavelength at about 535 nm and a broad FWHM about 260 nm. Moreover, the EL intensity of an ACW TFLED increased with an AC frequency of up to 180 kHz and, then, decreased rapidly and became very weak as the frequency was up to about 500 kHz. View full abstract»

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  • A MOS Image Sensor With a Digital-Microlens

    Publication Year: 2008 , Page(s): 986 - 991
    Cited by:  Papers (2)  |  Patents (5)
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (930 KB) |  | HTML iconHTML  

    We have developed a MOS image sensor with digital-microlenses (DMLs), each of which has an effective refractive index realized by variation of the subwavelength separations between the concentric SiO2 ring walls. The effective refractive index profiles are optimized for the location of each pixel. The light-collection efficiency of the image sensor is twice as high as that of a conventional image sensor because of the enhanced light acceptance in the periphery. A 2.2-mum pitch 3-megapixel MOS image sensor based on the DML technology exhibited excellent uniformity of the light-collection efficiency across the image area, even for light with a very large incident angle, i.e., over 45deg. The DML promises new levels of performance of image sensors. View full abstract»

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  • The Operation Characteristics of an Alternating Current Plasma Display Panel With Si-Doped MgO Protecting Layer

    Publication Year: 2008 , Page(s): 992 - 996
    Cited by:  Papers (3)
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (542 KB) |  | HTML iconHTML  

    In this paper, the operation characteristics of an ac plasma display panel (PDP) with Si-doped MgO protecting layer are investigated. The test panels are fabricated with the protecting layers of conventional MgO and Si-doped MgO, and the operation voltage margin, luminous efficacy, and address discharge time lag are observed. Even though the test panel with Si-doped MgO protecting layer showed lower operation voltages, higher luminous efficacy, and shorter statistical discharge time lag, its addressing discharge characteristics become deteriorated as the scanning time is increased from the end time of the reset period. The photon-induced surface conductivity increased by Si doping into MgO, and surface charges on the Si-doped MgO protecting layer showed faster decay characteristics compared to those on the conventional one. It is believed that the impurity doping into the protecting layer can improve the short-period characteristics of an ac PDP, but the long-term stability of surface charge retention is deteriorated. View full abstract»

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  • Gate Oxide Wear-Out and Breakdown Effects on the Performance of Analog and Digital Circuits

    Publication Year: 2008 , Page(s): 997 - 1004
    Cited by:  Papers (20)  |  Patents (1)
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (623 KB) |  | HTML iconHTML  

    To investigate the impact of gate oxide degradation and breakdown (BD) on complimentary metal-oxide-semiconductor circuit functionality, an accurate description of the electrical characteristics of the stressed devices, which can be included in circuit simulators, is needed. In this paper, a description of the stressed device performance that considers, on the one hand, the variation of the channel current and, on the other, the increase in the gate current due to the oxide degradation and BD is presented, which is able to account for different levels of oxide damage. The parameters extracted from device experimental data have been introduced in a circuit simulator to evaluate the effect of the oxide degradation and BD on simple analog (current mirror) and digital [reset set (RS) latches] circuits. The impact of the increase in the gate leakage current and the variation of the conduction along the metal-oxide-semiconductor field-effect transistor channel due to the oxide degradation on the circuit performances has been separately analyzed. View full abstract»

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  • Modeling and Analysis of the Asymmetric Source/Drain Extension CMOS Transistors for Nanoscale Technologies

    Publication Year: 2008 , Page(s): 1005 - 1012
    Cited by:  Papers (2)  |  Patents (1)
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (704 KB) |  | HTML iconHTML  

    The asymmetric source/drain extension (ASDE) transistor can be a suitable option because of improved short channel effects in technology nodes beyond 32 nm. In this paper, we have analyzed the impact of asymmetric drain extension reduction on the device metrics, namely, gate-to-drain capacitance, drain current, subthreshold leakage, and gate tunneling leakage current. Also, analytical models have been developed to model the effect of the ASDE devices. Based on our proposed analytical model, SPICE-compatible transistor models have been developed to include the ASDE device structure as possible design options. With our SPICE-compatible transistor models, large-scale circuit simulation can be performed to evaluate the benefits and the overheads associated with the ASDE devices. It is observed from circuit simulations that there is an optimal drain extension length which is different from the source extension length. With the ASDE devices, the circuit power delay product can effectively be reduced by almost 35% with respect to the conventional symmetric devices. View full abstract»

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  • The Tunnel Source (PNPN) n-MOSFET: A Novel High Performance Transistor

    Publication Year: 2008 , Page(s): 1013 - 1019
    Cited by:  Papers (45)
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (313 KB) |  | HTML iconHTML  

    As MOSFET is scaled below 90 nm, many daunting challenges arise. Short-channel effects (SCEs; drain-induced barrier lowering and VTHmiddotrolloff), off-state leakage, parasitic capacitance, and resistance severely limit the performance of these transistors. New device innovations are essential to overcome these difficulties. In this paper, we propose the concept of a novel tunnel source (PNPN) n-MOSFET based on the principle of band-to- band tunneling. It is found that the PNPN n-MOSFET has the potential of steep subthreshold swing and improved Ion in addition to immunities against SCEs. Therefore, such a PNPN n-MOSFET can overcome the ever-degrading on-off characteristics of the deeply scaled conventional MOSFET. The design of the PNPN n-MOSFET was extensively examined using simulations. Devices with source-side tunneling junctions were fabricated on bulk substrates using spike anneal, and the experimental data is presented. View full abstract»

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  • Modeling of V_{\rm th} Shift in nand Flash-Memory Cell Device Considering Crosstalk and Short-Channel Effects

    Publication Year: 2008 , Page(s): 1020 - 1026
    Cited by:  Papers (13)
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (1006 KB) |  | HTML iconHTML  

    A threshold-voltage (Vth) shift of sub-100-nm NAND flash-memory cell transistors was modeled systematically, and the modeling was verified by comparing with the data from measurement and 3-D device simulation. The Vth shift of the NAND flash-memory cell was investigated by changing parameters such as gate length, width, drain voltage, dielectric material between cells, space between cells, lightly doped-drain depth, and adjacent-cell bias. The proposed model covers two dominant device physics: capacitance coupling effect between adjacent cells and short-channel effect. Our model showed an accurate prediction of the Vth shift of NAND flash-memory array and a good agreement with the data from simulation and measurement. View full abstract»

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  • Electrical Properties of Low-Temperature-Compatible P-Channel Polycrystalline-Silicon TFTs Using High- \kappa Gate Dielectrics

    Publication Year: 2008 , Page(s): 1027 - 1034
    Cited by:  Papers (5)
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (1053 KB) |  | HTML iconHTML  

    In this paper, we describe a systematic study of the electrical properties of low-temperature-compatible p-channel polycrystalline-silicon thin-film transistors (poly-Si TFTs) using HfO2 and HfSiOx, high-k gate dielectrics. Because of their larger gate capacitance density, the TFTs containing the high-k gate dielectrics exhibited superior device performance in terms of higher Ion/Ioff current ratios, lower subthreshold swings (SSs), and lower threshold voltages (Vth), relative to conventional deposited-SiO2, albeit with slightly higher OFF-state currents. The TFTs incorporating HfSiOx, as the gate dielectric had ca. 1.73 times the mobility (muFE) relative to that of the deposited-SiO2 TFTs; in contrast, the HfO2 TFTs exhibited inferior mobility. We investigated the mechanism for the mobility degradation in these HfO2 TFTs. The immunity of the HfSiOx, TFTs was better than that of the HfO2 TFTs-in terms of their Vth shift, SS degradation, muFE degradation, and drive current deterioration-against negative bias temperature instability stressing. Thus, we believe that HfSiOx, rather than HfO2, is a potential candidate for use as a gate-dielectric material in future high-performance poly-Si TFTs. View full abstract»

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  • A New Method to Determine Effective Lateral Doping Abruptness and Spreading-Resistance Components in Nanoscale MOSFETs

    Publication Year: 2008 , Page(s): 1035 - 1041
    Cited by:  Papers (2)
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (1145 KB) |  | HTML iconHTML  

    A comprehensive technique for the accurate extraction of the effective lateral doping abruptness and the spreading-resistance components in source/drain extension (EXT) regions is presented by FET on-resistance characterization and physical resistance modeling. The spreading-resistance components under EXT-to-gate overlap, and spacer regions are successfully correlated to the lateral EXT doping abruptness by the relationship between on-resistance and overlap capacitance response measured from 90-nm-node silicon-on-insulator MOSFETs. The accurate determination of lateral doping abruptness is found to be essential for linking the external spreading resistance to intrinsic short-channel device characteristics. View full abstract»

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  • Ultralow-Thermal-Budget CMOS Process Using Flash-Lamp Annealing for 45 nm Metal/High- k FETs

    Publication Year: 2008 , Page(s): 1042 - 1049
    Cited by:  Papers (2)  |  Patents (1)
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (918 KB) |  | HTML iconHTML  

    This paper describes a fabrication process that uses flash-lamp annealing (FLA) and the characteristics of the CMOS transistors that are constructed with an ultralow-thermal- budget process tuned for 45-nm metal/high-k FETs. FLA enhances the drivability of pFETs with the solid-phase epitaxial (SPE) extension junction, but reducing the thermal budget deteriorates the poly-gate depletion and the electron mobility. Metal gate, however, prevents the depletion problem and leads to higher drain currents and better threshold-voltage (VTH) roll-offs when processed with tilted extension implantation combined with SPE + FLA than when processed with untilted extension implantation combined with spike rapid thermal annealing. Reducing the thermal budget is also effective in obtaining low VTH values in p-metal/HfSiON gate because of the reduced vacancy formation. Moreover, cluster-boron implantation for pFETs has superiority over monomer-boron implantation with Ge postamorphous implantation in terms of VTH roll-offs and Ion-Ioff's if FLA is used as activation. The superior electrical characteristics of full-metal- gate HfSiON transistors whose gate length is less than 50 nm, which are fabricated by using the FLA process, are demonstrated. View full abstract»

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  • Nonuniform Mobility-Enhancement Techniques and Their Impact on Device Performance

    Publication Year: 2008 , Page(s): 1050 - 1057
    Cited by:  Papers (6)
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (797 KB) |  | HTML iconHTML  

    Nowadays, process-induced stress is the preferential industrial method to enhance circuit performances. One of the most popular techniques is the strain induced by contact etch-stop layer. This technology induces a drain-current enhancement which depends on the device dimensions. This strong behavior has already been reported in the literature. In this paper, we propose a simple semianalytical physical model to understand the origin of this dependence and to highlight the physical limitations of the stress techniques. With this model, after a calibration, it would be possible to predict the MOSFET performance for a given transistor gate length. This approach is validated by experimental data and explains the reduction of the drain-current enhancement that is observed for ultrasmall gate-length MOSFET. View full abstract»

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  • Modeling and Layout Optimization of Differential Inductors for Silicon-Based RFIC Applications

    Publication Year: 2008 , Page(s): 1058 - 1066
    Cited by:  Papers (3)
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (755 KB) |  | HTML iconHTML  

    A scalable RF differential inductor model has been developed, enabling device performance versus layout size tradeoffs and optimization as well as accurate circuit predictions. Comparing inductors with identical inductance values up to an operating frequency of 10 GHz, large conductor width designs are found to yield good performance for inductors with small inductance values. As differential inductance or operating frequency increases, interactions between metallization resistive and substrate losses discourage the use of large widths as it consumes silicon area and degrades device performance. View full abstract»

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  • Nonuniform RF Overstress in High-Power Transistors and Amplifiers

    Publication Year: 2008 , Page(s): 1067 - 1073
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (600 KB) |  | HTML iconHTML  

    Nonuniform light emission from power transistors at 2-3-dB compression levels has been imaged using a microscope- mounted camera. The nonuniformity depends on the device lateral geometry, load impedance, dc and radio frequency (RF) conditions, and the negative gate current, which is a result of the RF-induced impact ionization in the transistors. Numerical simulations demonstrated a nonuniform distribution of the RF overstress in the transistors under the same conditions. The simulations indicate that the nonuniformity in the light intensity may be attributed to the RF-induced voltage overstress. Therefore, the observed light emission may be used as a direct and contactless monitor of the RF-induced overstress in transistors and power amplifiers. View full abstract»

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  • Matching the Transconductance Characteristics of CMOS ISFET Arrays by Removing Trapped Charge

    Publication Year: 2008 , Page(s): 1074 - 1079
    Cited by:  Papers (23)  |  Patents (69)
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (813 KB) |  | HTML iconHTML  

    This paper presents an approach for matching the transconductance characteristics of CMOS ISFET arrays by removing trapped charge. We describe how to design arrays of floating-gate ISFETs so that ultraviolet (UV) radiation and bulk-substrate biasing can be used to remove the random amount of trapped charge that accumulates on the gates during fabrication. The approach is applied directly to a prototype single-chip 2 2 array of ISFETs, which is designed and fabricated in a standard 0.35- CMOS process. By considering the transconductance characteristics of the 2 2 array before and after UV exposure, it is shown that the response can be matched after 10 h and that the ISFET threshold voltages converge to an equilibrium value of approximately 1 V. After matching, it is found that the ISFET array has a measured sensitivity of 46 mV/pH and can successfully image a change in the pH of a homogeneous electrolyte solution. View full abstract»

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  • Analytical Model of Amorphous Layer Thickness Formed by High-Tilt-Angle As Ion Implantation

    Publication Year: 2008 , Page(s): 1080 - 1084
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (364 KB) |  | HTML iconHTML  

    We previously proposed a compact model of amorphous layer thickness over a wide range of ion implantation conditions using a vertical ion implantation profile parameter database. We also proposed a new parameter for the through dose. We extended the model to any tilt angle for ion implantation using one more parameter for the lateral straggling of the ion implantation profile. View full abstract»

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  • Strained CMOS Devices With Shallow-Trench-Isolation Stress Buffer Layers

    Publication Year: 2008 , Page(s): 1085 - 1089
    Cited by:  Papers (4)  |  Patents (1)
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (646 KB) |  | HTML iconHTML  

    In this brief, shallow-trench-isolation (STI) stress buffer techniques, including sidewall stress buffer and channel surface buffer layers, are developed to reduce the impact of compressive STI stress on the mobility of advanced n-type MOS (NMOS) devices. Our investigation shows that a 7% driving current gain at an NMOS device has been achieved, whereas no degradation at a p-type MOS (PMOS) device was observed. The same junction leakage at both the NMOS and PMOS devices was maintained. A stress relaxation model with simulation is thus proposed to account for the enhanced transport characteristics. View full abstract»

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  • Micro-Raman/Infrared Temperature Monitoring of Gunn Diodes

    Publication Year: 2008 , Page(s): 1090 - 1093
    Cited by:  Papers (3)
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (280 KB) |  | HTML iconHTML  

    Temperature measurements have been made on Gunn diode samples, using both infrared (IR) and micro-Raman spectroscopy. Micro-Raman spectroscopy was used to give high-resolution temperature measurements on the active transit region of the Gunn diode. These were directly compared with IR thermal measurements made across the mesa region and also on the metallized top contact of the diode. View full abstract»

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  • Corrections to “a three-dimensional simulation study of the performance of carbon nanotube field-effect transistors with doped reservoirs and realistic geometry” [Aug 06 1782-1788]

    Publication Year: 2008 , Page(s): 1094 - 1095
    Cited by:  Papers (2)
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (124 KB) |  | HTML iconHTML  

    In the above titled paper (ibid., vol. 53, no. 8, pp. 1782-1788, Aug 06), there are some errors in the results. This errata corrects Figs. 5-11, and 13 of the original paper and adds Fig. 14. View full abstract»

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Aims & Scope

IEEE Transactions on Electron Devices publishes original and significant contributions relating to the theory, modeling, design, performance and reliability of electron and ion integrated circuit devices and interconnects.

 

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Meet Our Editors

Acting Editor-in-Chief

Dr. Paul K.-L. Yu

Dept. ECE
University of California San Diego