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IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems

Issue 4 • April 2008

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  • Table of contents

    Publication Year: 2008, Page(s):C1 - C4
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  • IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems publication information

    Publication Year: 2008, Page(s): C2
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  • Statistical Timing Analysis: From Basic Principles to State of the Art

    Publication Year: 2008, Page(s):589 - 607
    Cited by:  Papers (170)  |  Patents (2)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (622 KB) | HTML iconHTML

    Static-timing analysis (STA) has been one of the most pervasive and successful analysis engines in the design of digital circuits for the last 20 years. However, in recent years, the increased loss of predictability in semiconductor devices has raised concern over the ability of STA to effectively model statistical variations. This has resulted in extensive research in the so-called statistical ST... View full abstract»

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  • Guest Editorial

    Publication Year: 2008, Page(s):608 - 609
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  • Variability-Driven Formulation for Simultaneous Gate Sizing and Postsilicon Tunability Allocation

    Publication Year: 2008, Page(s):610 - 620
    Cited by:  Papers (16)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (286 KB) | HTML iconHTML

    Process variations cause design performance to become unpredictable in deep submicrometer technologies. Several statistical techniques (timing analysis, gate sizing, and buffer insertion) have been proposed to counter these variations during the optimization phase of the design flow to get a better timing yield. Another interesting approach to improve the timing yield is postsilicon-tunable (PST) ... View full abstract»

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  • Is Your Layout-Density Verification Exact?—A Fast Exact Deep Submicrometer Density Calculation Algorithm

    Publication Year: 2008, Page(s):621 - 632
    Cited by:  Papers (5)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (962 KB) | HTML iconHTML

    As the device shapes keep shrinking, the designs are more sensitive to manufacturing processes. In order to improve performance predictability and yield, mask-layout uniformity/evenness is highly desired, and it is usually measured by the feature densities within defined feasible ranges determined by the manufacturing-process design rules. To address the density-control problem, one fundamental pr... View full abstract»

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  • Fast Dummy-Fill Density Analysis With Coupling Constraints

    Publication Year: 2008, Page(s):633 - 642
    Cited by:  Papers (10)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (1009 KB) | HTML iconHTML

    In modern very large scale integration manufacturing processes, dummy fills are widely used to adjust local metal density in order to improve layout uniformity and yield optimization. However, the introduction of a large amount of dummy features also affects wire electrical properties. In this paper, we propose the first coupling-constrained dummy-fill analysis algorithm which identifies feasible ... View full abstract»

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  • Obstacle-Avoiding Rectilinear Steiner Tree Construction Based on Spanning Graphs

    Publication Year: 2008, Page(s):643 - 653
    Cited by:  Papers (23)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (923 KB) | HTML iconHTML

    Given a set of pins and a set of obstacles on a plane, an obstacle-avoiding rectilinear Steiner minimal tree (OARSMT) connects these pins, possibly through some additional points (called the Steiner points), and avoids running through any obstacle to construct a tree with a minimal total wirelength. The OARSMT problem becomes more important than ever for modern nanometer IC designs which need to c... View full abstract»

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  • Effective Wire Models for X-Architecture Placement

    Publication Year: 2008, Page(s):654 - 658
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (393 KB) | HTML iconHTML

    In this paper, we derive the X-half-perimeter wirelength (XHPWL) model for X-architecture placement and explore the effects of three different wire models on X-architecture placement, including the Manhattan-half-perimeter wirelength (MHPWL) model, the XHPWL model, and the X-Steiner wirelength (XStWL) model. For min-cut partitioning placement, we apply the XHPWL and XStWL models to the generalized... View full abstract»

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  • Technology Mapping and Cell Merger for Asynchronous Threshold Networks

    Publication Year: 2008, Page(s):659 - 672
    Cited by:  Papers (13)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (432 KB) | HTML iconHTML

    A key challenge in using timing-robust asynchronous circuit styles is the lack of automated optimization techniques. In this paper, technology mapping and cell merger algorithms for asynchronous threshold networks are introduced. The cell merger problem is a restricted form of technology mapping where only adjacent cells are merged. The two algorithms can each target either delay or area, or a com... View full abstract»

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  • Bitmask-Based Code Compression for Embedded Systems

    Publication Year: 2008, Page(s):673 - 685
    Cited by:  Papers (28)  |  Patents (3)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (711 KB) | HTML iconHTML

    Embedded systems are constrained by the available memory. Code-compression techniques address this issue by reducing the code size of application programs. It is a major challenge to develop an efficient code-compression technique that can generate substantial reduction in code size without affecting the overall system performance. We present a novel code-compression technique using bitmasks, whic... View full abstract»

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  • Slack Allocation and Routing to Improve FPGA Timing While Repairing Short-Path Violations

    Publication Year: 2008, Page(s):686 - 697
    Cited by:  Papers (6)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (583 KB) | HTML iconHTML

    This paper presents the first published algorithm to simultaneously optimize both short- and long-path timing in a field-programmable gate array (FPGA): the routing cost valleys (RCV) algorithm. RCV consists of the following two components: a new slack-allocation algorithm that determines both a minimum and a maximum delay budget for each circuit connection and a new router that strives to meet an... View full abstract»

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  • GfXpress: A Technique for Synthesis and Optimization of $hbox{GF}(2^{m})$ Polynomials

    Publication Year: 2008, Page(s):698 - 711
    Cited by:  Papers (7)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (656 KB) | HTML iconHTML

    This paper presents an efficient technique for synthesis and optimization of the polynomials over GF(2m), where to is a nonzero positive integer. The technique is based on a graph-based decomposition and factorization of the polynomials, followed by efficient network factorization and optimization. A technique for efficiently computing the coefficients of the polynomials over GF(pm... View full abstract»

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  • Structural Macromodeling of Analog Circuits Through Model Decoupling and Transformation

    Publication Year: 2008, Page(s):712 - 725
    Cited by:  Papers (8)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (1419 KB) | HTML iconHTML

    This paper presents a systematic methodology for developing structural macromodels expressing the linear and weakly nonlinear performance of analog circuits. The models are in the frequency domain. The methodology includes two steps. First, building-block behavioral (BBB) concept is used to describe the basic building blocks of a circuit, and a decoupling technique is used to generate uncoupled BB... View full abstract»

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  • Fashion: A Fast and Accurate Solution to Global Routing Problem

    Publication Year: 2008, Page(s):726 - 737
    Cited by:  Papers (4)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (1285 KB) | HTML iconHTML

    This paper presents a fast and accurate solution, namely Fashion, to routability-driven global routing problem. Fashion is based on two efficient yet effective techniques: 1) dynamic pattern routing (DPR) and 2) movable-segment-driven DPR. These two techniques enable Fashion to explore large solution space to achieve high routability with low time complexity. Compared with BoxRouter, Fashion has a... View full abstract»

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  • Power Grid Analysis and Optimization Using Algebraic Multigrid

    Publication Year: 2008, Page(s):738 - 751
    Cited by:  Papers (20)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (577 KB) | HTML iconHTML

    This paper presents a class of power grid analysis and optimization techniques, all of which are based on the algebraic-multigrid (AMG) method. First, a new AMG-based reduction scheme is proposed to improve the efficiency of reducing the problem size for power grid analysis and optimization. Next, with the proposed reduction technique, a fast transient-analysis method is developed and extended to ... View full abstract»

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  • Quantum Circuit Placement

    Publication Year: 2008, Page(s):752 - 763
    Cited by:  Papers (12)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (400 KB) | HTML iconHTML

    We study the problem of the practical realization of an abstract quantum circuit when executed on a quantum hardware. By practical, we mean adapting the circuit to particulars of the physical environment which restricts/complicates the establishment of certain direct interactions between qubits. This is a quantum version of the classical circuit placement problem. We study the theoretical aspects ... View full abstract»

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  • An Anytime Algorithm for Generalized Symmetry Detection in ROBDDs

    Publication Year: 2008, Page(s):764 - 777
    Cited by:  Papers (2)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (539 KB) | HTML iconHTML

    Detecting symmetries have many applications in logic synthesis, which include, among other things, technology mapping, deciding equivalence of Boolean functions when the input correspondence is unknown, and finding support-reducing bound sets. Mishchenko showed how to efficiently detect symmetries in reduced ordered binary decision diagrams (ROBDDs) without the need for checking equivalence of all... View full abstract»

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  • IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems Information for authors

    Publication Year: 2008, Page(s): 778
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  • 2008 IEEE Asia Pacific Conference on Circuits and Systems

    Publication Year: 2008, Page(s): 779
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    Publication Year: 2008, Page(s): 780
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  • IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems society information

    Publication Year: 2008, Page(s): C3
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Aims & Scope

The purpose of this Transactions is to publish papers of interest to individuals in the area of computer-aided design of integrated circuits and systems composed of analog, digital, mixed-signal, optical, or microwave components.

Full Aims & Scope

Meet Our Editors

Editor-in-Chief

VIJAYKRISHNAN NARAYANAN
Pennsylvania State University
Dept. of Computer Science. and Engineering
354D IST Building
University Park, PA 16802, USA
vijay@cse.psu.edu