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IEEE Transactions on Computers

Issue 11 • Date Nov. 1992

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Displaying Results 1 - 15 of 15
  • Comments on "Tolerance of double-loop computer networks to multimode failures" by H. Masuyama and T. Ichimori

    Publication Year: 1992, Page(s):1488 - 1490
    Cited by:  Papers (4)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (255 KB)

    H. Masuyama and T. Ichimori (see IEEE Trans. Comput., vol.38, no.5, p.738-41, 1989) quantitatively evaluated the ability of a class of double-loop networks called forward-loop-backward-hop (FLBH) networks to tolerate node failures. Their approach was based on the enumeration of all possible sets of failures. The authors prove that their results are incorrect and demonstrate that it is difficult to... View full abstract»

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  • The reliability of systems with two levels of fault tolerance: the return of the `birthday surprise'

    Publication Year: 1992, Page(s):1490 - 1496
    Cited by:  Papers (2)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (456 KB)

    The reliability of systems that employ fault tolerance at two different hierarchical levels is considered. It is assumed that the system consists of a two-dimensional array of components. Each component is reliable as long as it has been afflicted by no more than t faults; when t+1 faults occur in a particular component, the component ceases to be reliable. Furthermore, the syste... View full abstract»

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  • A polynomial algorithm for balancing acyclic data flow graphs

    Publication Year: 1992, Page(s):1380 - 1385
    Cited by:  Papers (6)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (516 KB)

    Data flow machines whose task graphs are acyclic can be transformed into synchronous machines, thereby increasing pipelining and throughput. This is achieved by introducing delays or buffers on certain lines, so that the resulting graph is balanced, i.e., travel times along any two paths with common endpoints are the same. The buffer assignment problem is how to balance a rooted acyclic data flow ... View full abstract»

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  • Intermittent fault diagnosis in multiprocessor systems

    Publication Year: 1992, Page(s):1430 - 1441
    Cited by:  Papers (9)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (928 KB)

    The authors present and analyze a probabilistic model for the self-diagnosis capabilities of a multiprocessor system. In this model an individual processor fails with probability p and a nonfaulty processor testing a faulty processor detects a fault with probability q. This models the situation where processors can be intermittently faulty or the situation where tests are not cap... View full abstract»

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  • On the delay-sensitivity of gate networks

    Publication Year: 1992, Page(s):1349 - 1360
    Cited by:  Papers (13)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (1000 KB)

    In classical switching theory, asynchronous sequential circuits are operated in the fundamental mode. In this mode, a circuit is started in a stable state, and then the inputs are changed to cause a transition to another stable state. The inputs are not allowed to change again until the entire circuit has stabilized. In contrast to this, delay-insensitive circuits-the correctness of which is insen... View full abstract»

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  • Design and analysis of a generalized architecture for reconfigurable m-ary tree structures

    Publication Year: 1992, Page(s):1465 - 1478
    Cited by:  Papers (1)  |  Patents (1)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (1080 KB)

    A generalized architecture is presented for reconfigurable m -ary tree structures, where m is any integer >1. The approach is based on a generalized multistage interconnection network (MIN), which is a generalization of the augmented shuffle-exchange MIN introduce by the authors previously (1990) for obtaining reconfigurable binary tree structures. The generalized architecture... View full abstract»

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  • Performance analysis of client-server storage systems

    Publication Year: 1992, Page(s):1442 - 1452
    Cited by:  Papers (12)  |  Patents (9)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (828 KB)

    The performance analysis of a system in which storage is provided by a file server node on a network of client processors is discussed. The server controls a hierarchy of storage devices, and provides all the necessary file management functions. The clients are large mainframe systems that have their own local storage devices. The movement of files among the various storage levels is managed by a ... View full abstract»

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  • Efficient distributed algorithms for self testing of multiple processor systems

    Publication Year: 1992, Page(s):1397 - 1409
    Cited by:  Papers (4)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (1028 KB)

    Multiple processor systems allow both highly reliable and highly fast service. Distributed self-test algorithms that attempt to improve both the reliability and the performance of these systems are proposed. In these algorithms, reliability is improved by considering the distributed mode of control and assigning processors to test each other periodically for the diagnosis and isolation of the faul... View full abstract»

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  • On self-diagnosable multiprocessor systems: diagnosis by the comparison approach

    Publication Year: 1992, Page(s):1386 - 1396
    Cited by:  Papers (71)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (912 KB)

    The diagnosability and diagnosis problems for a model introduced by J. Maeng and M. Malek (1981) of a self-diagnosable multiprocessor system where processors compare the results of tasks performed by other processors in the system are analyzed. A set of criteria is given for determining whether the faulty processors in the system can be diagnosed on the basis of the comparisons, and a polynomial-t... View full abstract»

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  • On a class of rearrangeable networks

    Publication Year: 1992, Page(s):1361 - 1379
    Cited by:  Papers (18)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (1312 KB)

    Benes networks are nonblocking rearrangeable networks that can realize arbitrary permutations without conflict. A class of 2 logb N stage networks which are equivalent to the Benes networks is introduced. Networks in this class can be either symmetric or asymmetric in their structure, regular or irregular in their interstage connections, and even, 2 logb N ... View full abstract»

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  • New fault tolerant techniques for residue number systems

    Publication Year: 1992, Page(s):1453 - 1464
    Cited by:  Papers (5)  |  Patents (1)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (1080 KB)

    Previously proposed error detection algorithms for the residue number system require a complete recombination. A weighted approximation via the Chinese remainder theorem is shown to be sufficient to detect 100% of single errors. This makes real-time single-error diagnosis possible, which involves up to N+2 iterations of detection (N is the number of nonredundant channels). One ap... View full abstract»

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  • Evaluation of A+B=K conditions without carry propagation

    Publication Year: 1992, Page(s):1484 - 1488
    Cited by:  Papers (20)  |  Patents (38)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (384 KB)

    The response time of parallel adders is mainly determined by the carry propagation delay. The evaluation of conditions of the type A +B=K is addressed. Although an addition is involved in the comparison, it is shown that it can be evaluated without carry propagation, thus drastically reducing the computation time. Dependencies produced by branches degrade the performance... View full abstract»

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  • A cost-effective combining structure for large-scale shared-memory multiprocessors

    Publication Year: 1992, Page(s):1420 - 1429
    Cited by:  Papers (5)  |  Patents (2)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (944 KB)

    A cost-effective combining structure to alleviate hot-spot contention is proposed. The key idea is that the combining function is separated from the routing function, so that a binary tree-based combining configuration becomes feasible. The combining element for realizing the new structure has only one wait buffer and one combining logic, involving less hardware than the element used in earlier co... View full abstract»

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  • UPP graphs and UMFA networks-architecture for parallel systems

    Publication Year: 1992, Page(s):1479 - 1483
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (432 KB)

    A graph with unique path property (UPP) has 2n vertices and a unique path of length n between every two vertices. These graphs are very important in the design of architectures and algorithms for interconnection networks. Given two UPP graphs, an algorithm is introduced to determine isomorphism between the graphs. A construction is given for nonisomorphic UPP graphs and a lower... View full abstract»

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  • Asymptotically optimal broadcasting and gossiping in faulty hypercube multicomputers

    Publication Year: 1992, Page(s):1410 - 1419
    Cited by:  Papers (13)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (980 KB)

    Various algorithms for reliable broadcasting (one-to-all) and gossiping (all-to-all) in faulty n-dimensional hypercube multicomputers are described and analyzed. For a broadcast (resp., a gossiping algorithm), the goal is that each processor receives complete information from the source (resp., from all the other processors) even in the presence of faults. One of the main characteristics ... View full abstract»

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The IEEE Transactions on Computers is a monthly publication with a wide distribution to researchers, developers, technical managers, and educators in the computer field.

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Meet Our Editors

Editor-in-Chief
Paolo Montuschi
Politecnico di Torino
Dipartimento di Automatica e Informatica
Corso Duca degli Abruzzi 24 
10129 Torino - Italy
e-mail: pmo@computer.org