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Computers, IEEE Transactions on

Issue 1 • Date Jan 1989

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Displaying Results 1 - 13 of 13
  • Resource sharing interconnection networks in multiprocessors

    Publication Year: 1989 , Page(s): 115 - 129
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (1364 KB)  

    Circuit-switched interconnection networks for resource sharing in multiprocessors are studied. Resource scheduling in systems with such an interconnection network entails the efficient search for a mapping from requesting processors to free resources such that circuit blockages in the network are minimized and resources are maximally used. The optimal mapping is obtained by transforming the scheduling problems into various network flow problems to which existing algorithms can be applied. A distributed architecture to realize a maximum flow algorithm using token propagations is described. The method is applicable to any general loop-free network configuration in which the requesting processors and free resources can be partitioned into two disjoint subsets View full abstract»

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  • On the size of PLAs required to realize binary and multiple-valued functions

    Publication Year: 1989 , Page(s): 82 - 98
    Cited by:  Papers (10)
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (1124 KB)  

    Upper and lower bounds are shown for the average number of product terms required in the minimal realization, as a function of the number of nonzero output values. The variance, in addition to the bounds, allows conclusions to be drawn about how PLA size determines the set of realizable functions. Although the bounds are most accurate when there are few nonzero values, they are adequate for analyzing commercially available PLAs. The analysis shows that, for all but one commercially available PLA, the number of nonzero values is a statistically meaningful criterion for determining whether or not a given function is likely to be realized View full abstract»

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  • Product form approximations for queueing networks with multiple servers and blocking

    Publication Year: 1989 , Page(s): 99 - 114
    Cited by:  Papers (10)
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (1084 KB)  

    It is shown that the equilibrium-state probabilities for this type of blocking queuing network have an approximate product-form solution, which is based on normalizing the infeasible states that violate station capacities. To obtain the throughput values, a state-space transformation is introduced. This concept is based on finding a nonblocking network with an appropriate total number of jobs of which the number of feasible states is equal or approximately equal to the number of feasible states in the blocking queuing network. This guarantees that the Markov processes describing the evolution networks over time have approximately the same structure, so the throughputs of both systems are approximately equal. The approximations are validated by executing several examples and comparing them with simulation results View full abstract»

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  • An empirical analysis of the Lilith instruction set

    Publication Year: 1989 , Page(s): 156 - 158
    Cited by:  Papers (1)  |  Patents (1)
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (320 KB)  

    A static analysis of the instructions used to implement all of the system software on the Lilith computer is described. The results are compared to those of a similar analysis performed on the Mesa instruction set architecture. The data provide a good illustration of how code generation strategies and language usage can affect opcode statistics, even for machines with similar architectures View full abstract»

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  • Code optimization for tagged-token dataflow machines

    Publication Year: 1989 , Page(s): 4 - 14
    Cited by:  Papers (5)  |  Patents (4)
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (872 KB)  

    The efficiency of dataflow code generated from a high-level language can be considerably improved by both conventional and dataflow-specific optimizations. Such techniques are used in implementing the single-assignment language SISAL on the Manchester Dataflow Machine. The quality of code generated for numeric applications can be measured in terms of the ratio of total number of instructions executed to floating-point operations: the MIPS/MFLOPS ratio. Relevant features of the general-purpose single-assignment language SISAL and the Manchester Dataflow Machine are introduced. An assessment of the initial SISAL implementation shows it to be very expensive. A range of optimizations is then described View full abstract»

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  • An orthogonal multiprocessor for parallel scientific computations

    Publication Year: 1989 , Page(s): 47 - 61
    Cited by:  Papers (28)
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (1164 KB)  

    An architecture called an orthogonal multiprocessor (OMP) is proposed. This OMP architecture has a simplified busing structure and partially shared memory and compares very favorably with fully shared-memory multiprocessors using crossbar switches, multiple buses, or multistage networks. The higher performance comes mainly from significantly increased memory bandwidth, fully exploited parallelism, reduced communication overhead, and lower hardware control complexities. Parallel algorithms being mapped include matrix arithmetic, linear system solver, FFT, array sorting, linear programming, and parallel PDE solutions. In most cases, linear speedup can be achieved on the OMP system. The OMP architecture provides linearly scalable performance and is well suited for building special-purpose scientific computers View full abstract»

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  • Primitive cellular automata, threshold decomposition, and ranked order operations

    Publication Year: 1989 , Page(s): 148 - 149
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (220 KB)  

    A connection between ranked filters and primitive cellular automata is discussed. Primitive cellular automata are those whose nodes comprise a single bit of state information. It is shown that these structures can perform ranked order operations on one-dimensional k -level signals by virtue of threshold decomposition. Extensions to the case of multidimensional signals are also possible View full abstract»

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  • Via assignment in single-row routing

    Publication Year: 1989 , Page(s): 142 - 148
    Cited by:  Papers (1)
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (540 KB)  

    Examines the via assignment problem that arises when the single-row routing approach to the interconnection problem is used. Some new complexity results and two new heuristics are obtained. Experimental results establish the superiority of the new heuristics over earlier ones View full abstract»

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  • The design, analysis and simulation of a fault-tolerant interconnection network supporting the fetch-and-add primitive

    Publication Year: 1989 , Page(s): 30 - 46
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (1548 KB)  

    The combining multistage interconnection network uses 4×4 switches as switching elements and introduces an extra stage of such switches and links to create four independent paths between any source-destination pair. Four copies of every message are sent through the network simultaneously. The scheduling discipline, the design of the switching elements to support the discipline, and the theoretical proof of correctness of the design constitute the key contributions of this study. Estimates are provided of various network parameters as a function of the workload, using analytical models and detailed network simulations. It is shown that the proposed design for fault tolerance is more cost-effective than the brute-force technique of having multiple copies of the network View full abstract»

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  • A family of new efficient arrays for matrix multiplication

    Publication Year: 1989 , Page(s): 149 - 155
    Cited by:  Papers (9)  |  Patents (1)
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (556 KB)  

    The authors present a regular iterative algorithm for matrix multiplication and show that several well-known matrix multiplication arrays are directly obtained from it, differing only in the choice of iteration vector. They then present a regular iterative algorithm for matrix multiplication using the S. Winograd method (1968) and show in detail how to derive one array from this algorithmic description. Other arrays in the same family can similarly be obtained for different choices of the iteration space. The new arrays compute the product of two matrices faster than available conventional arrays and use a smaller number of processor cells View full abstract»

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  • Multiple-way network partitioning

    Publication Year: 1989 , Page(s): 62 - 81
    Cited by:  Papers (136)  |  Patents (7)
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (1592 KB)  

    A multiple-block network partitioning algorithm adapted from a two-block iterative improvement partitioning algorithm is presented. This adaptation of the algorithm and of the level gain concept to multiple blocks seeks to improve the partition uniformly with respect to all blocks as oppose to making repeated uses of two-way partitioning. Appropriate data structures and a complexity analysis are presented, as well as experimental results. The experiments indicate that the optimal number of levels to use depends on the number of blocks and the net size and degree distributions of the network, but it varies little with the size of the network. In particular, higher levels are increasingly useful as the number of blocks in the partition increases. Theoretical results agree with the experimental results and form the basis for a predictor which, given a network and the desired number of blocks, approximates the optimal number of levels View full abstract»

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  • Criteria for selecting a variable in the construction of efficient decision trees

    Publication Year: 1989 , Page(s): 130 - 141
    Cited by:  Papers (3)
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (924 KB)  

    Two variable selection criteria are proposed for converting a decision table to a near-optimum decision tree in the sense of minimal average cost of testing. A criterion, Q, is introduced that is based on the potential of a decision table. The previously known criterion `loss' and Q are combined into a third criterion O. The performance of the three criteria is examined both theoretically and experimentally. Of most importance is that Q and O do not select a nonessential variable, while `loss' may do so. It is also shown that the performance of the three criteria is not worse than that of any other known heuristics, at least for a particular example. The algorithm requires at most O(L2 2L) operations, where L is the arity of an input table View full abstract»

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  • A general constructive approach to fault-tolerant design using redundancy

    Publication Year: 1989 , Page(s): 15 - 29
    Cited by:  Papers (20)  |  Patents (5)
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (1000 KB)  

    The use of redundancy to attain a fault-tolerant system design is described. Specifically, a general theory of redundancy is proposed that allows the design of fault-tolerant structures at the system-level, gate-level, or both. The theory accounts for classic approaches to redundant design such as TMR, NMR, and quadded and interwoven logics. It is shown that, by using mathematical block theory, it is possible to describe complex interconnections of redundant elements in a simple, straightforward fashion. Comparisons are made with other approaches to redundant design View full abstract»

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Aims & Scope

The IEEE Transactions on Computers is a monthly publication with a wide distribution to researchers, developers, technical managers, and educators in the computer field.

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Meet Our Editors

Editor-in-Chief
Paolo Montuschi
Politecnico di Torino
Dipartimento di Automatica e Informatica
Corso Duca degli Abruzzi 24 
10129 Torino - Italy
e-mail: pmo@computer.org