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IEEE Transactions on Very Large Scale Integration (VLSI) Systems

Issue 3 • Date March 2008

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Displaying Results 1 - 18 of 18
  • Table of contents

    Publication Year: 2008, Page(s): C1
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  • IEEE Transactions on Very Large Scale Integration (VLSI) Systems publication information

    Publication Year: 2008, Page(s): C2
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  • A Novel \Delta \Sigma Control System Processor and Its VLSI Implementation

    Publication Year: 2008, Page(s):217 - 228
    Cited by:  Papers (7)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (3025 KB) | HTML iconHTML

    This paper describes a novel control system processor architecture based on DeltaSigma modulation known as the DeltaSigma -CSP. The DeltaSigma -CSP utilizes 1-bit processing which is a new concept in digital control applications with the direct benefit of making multi-bit multiplication operations redundant. A simple conditional-negate-and-add (CNA) unit is instead used for operations in control l... View full abstract»

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  • Active Cache Emulator

    Publication Year: 2008, Page(s):229 - 240
    Cited by:  Papers (1)  |  Patents (2)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (1570 KB) | HTML iconHTML

    This paper presents the active cache emulator (ACE), a novel field-programmable gate-array (FPGA)-based emulator that models an L3 cache actively and in real-time. ACE leverages interactions with its host system to model the target system. Unlike most existing FPGA-based cache emulators that collect only memory traces from their host system, ACE provides feedback to its host by injecting delays to... View full abstract»

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  • Fast Estimation of Timing Yield Bounds for Process Variations

    Publication Year: 2008, Page(s):241 - 248
    Cited by:  Papers (5)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (449 KB) | HTML iconHTML

    With aggressive scaling down of feature sizes in VLSI fabrication, process variation has become a critical issue in designs. We show that two necessary conditions for the ldquomaxrdquo operation are actually not satisfied in the moment matching based statistical timing analysis approaches. We propose two correlation-aware block-based statistical timing analysis approaches that keep these necessary... View full abstract»

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  • Body Bias Voltage Computations for Process and Temperature Compensation

    Publication Year: 2008, Page(s):249 - 262
    Cited by:  Papers (23)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (703 KB) | HTML iconHTML

    With continued scaling into the sub-90-nm regime, the role of process, voltage, and temperature (PVT) variations on the performance of VLSI circuits has become extremely important. These variations can cause the delay and the leakage of the chip to vary significantly from their expected values, thereby affecting the yield. Circuit designers have proposed the use of threshold voltage modulation tec... View full abstract»

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  • System-Level Specification Testing Of Wireless Transceivers

    Publication Year: 2008, Page(s):263 - 276
    Cited by:  Papers (9)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (1726 KB) | HTML iconHTML

    This paper presents an efficient system-level manufacturing test methodology for wireless transceiver systems. Conventional system-level testing procedures incur large test times and require the use of multiple test hardware configurations for measuring frequency and modulation-domain performance specifications, e.g., system-gain, nonlinearity, noise-figure, channel power, adjacent-channel power-r... View full abstract»

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  • Write Disturbance Modeling and Testing for MRAM

    Publication Year: 2008, Page(s):277 - 288
    Cited by:  Papers (6)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (2111 KB) | HTML iconHTML

    The magnetic random access memory (MRAM) is considered one of the potential candidates that will replace current on-chip memories (RAM, EEPROM, and flash memory) in the future. The MRAM is fast and does not need a high supply voltage for read/write operations, and is compatible with the CMOS technology. It can also endure almost unlimited read/write cycles. These combined advantages of RAM and fla... View full abstract»

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  • Scalable QoS-Aware Memory Controller for High-Bandwidth Packet Memory

    Publication Year: 2008, Page(s):289 - 301
    Cited by:  Papers (2)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (712 KB) | HTML iconHTML

    This paper proposes a high-performance scalable quality-of-service (QoS)-aware memory controller for the packet memory where packet data are stored in network routers. A major challenge in the packet memory controller design is to make the design scalable. As the input and output bandwidth requirement and the number of output queues for routers increase, the memory system becomes a bottleneck that... View full abstract»

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  • A Power-Efficient and Self-Adaptive Prediction Engine for H.264/AVC Decoding

    Publication Year: 2008, Page(s):302 - 313
    Cited by:  Papers (21)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (2654 KB) | HTML iconHTML

    Prediction, including intra prediction and inter prediction, is the most critical issue in H.264/AVC decoding in terms of processing cycles and computation complexity. These two predictions demand a huge number of memory accesses and account for up to 80% of the total decoding cycles. In this paper, we present the design and VLSI implementation of a novel power-efficient and highly self-adaptive p... View full abstract»

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  • Joint Equalization and Coding for On-Chip Bus Communication

    Publication Year: 2008, Page(s):314 - 318
    Cited by:  Papers (7)  |  Patents (4)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (238 KB) | HTML iconHTML

    In this paper, we propose using joint equalization and coding to improve on-chip communication speeds by signaling at rates beyond the rate governed by resistance-capacitance (RC) delay of the interconnect. Operating beyond the RC limit introduces inter-symbol interference (ISI). We mitigate the effects of ISI by employing equalization. The proposed equalizer employs a variable threshold inverter ... View full abstract»

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  • Improved Accuracy Pseudo-Exponential Function Generator With Applications in Analog Signal Processing

    Publication Year: 2008, Page(s):318 - 321
    Cited by:  Papers (7)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (527 KB) | HTML iconHTML

    A new CMOS current-mode pseudo-exponential circuit based on the n-order Taylor series expansion will be presented. The most important advantage of the circuit with respect to the previously reported similar ones is the smaller value of the total computing error (under 0.3 dB), for a maximal output range of the proposed function generator greater than 40 dB. The total error could be very easily red... View full abstract»

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  • Speculative Carry Generation With Prefix Adder

    Publication Year: 2008, Page(s):321 - 326
    Cited by:  Papers (3)  |  Patents (1)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (704 KB) | HTML iconHTML

    A framework that generates formal prefix equations for speculative carry generation is presented. It is applicable to both normal carry and Ling carry adders and generates four forms of speculative carry generate prefix schemes (two forms for each carry case). For normal carry, one corresponds to an existing design and the other is newly introduced. For the Ling carry, both are newly proposed. View full abstract»

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  • A Novel Hybrid Parallel-Prefix Adder Architecture With Efficient Timing-Area Characteristic

    Publication Year: 2008, Page(s):326 - 331
    Cited by:  Papers (6)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (383 KB) | HTML iconHTML

    Two-operand binary addition is the most widely used arithmetic operation in modern datapath designs. To improve the efficiency of this operation, it is desirable to use an adder with good performance and area tradeoff characteristics. This paper presents an efficient carry-lookahead adder architecture based on the parallel-prefix computation graph. In our proposed method, we define the notion of t... View full abstract»

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  • Low Power Design of Precomputation-Based Content-Addressable Memory

    Publication Year: 2008, Page(s):331 - 335
    Cited by:  Papers (23)  |  Patents (2)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (246 KB) | HTML iconHTML

    Content-addressable memory (CAM) is frequently used in applications, such as lookup tables, databases, associative computing, and networking, that require high-speed searches due to its ability to improve application performance by using parallel comparison to reduce search time. Although the use of parallel comparison results in reduced search time, it also significantly increases power consumpti... View full abstract»

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  • In this issue - Technically

    Publication Year: 2008, Page(s): 336
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    Freely Available from IEEE
  • IEEE Transactions on Very Large Scale Integration (VLSI) Systems society information

    Publication Year: 2008, Page(s): C3
    Request permission for commercial reuse | PDF file iconPDF (25 KB)
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  • IEEE Transactions on Very Large Scale Integration (VLSI) Systems Information for authors

    Publication Year: 2008, Page(s): C4
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Aims & Scope

Design and realization of microelectronic systems using VLSI/ULSI technologies requires close collaboration among scientists and engineers in the fields of systems architecture, logic and circuit design, chips and wafer fabrication, packaging, testing, and systems applications. Generation of specifications, design, and verification must be performed at all abstraction levels, including the system, register-transfer, logic, circuit, transistor, and process levels. To address this critical area through a common forum, the IEEE Transactions on VLSI Systems was founded.

Full Aims & Scope

Meet Our Editors

Editor-in-Chief

Krishnendu Chakrabarty
Department of Electrical Engineering
Duke University
Durham, NC 27708 USA
Krish@duke.edu