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IEEE Transactions on Computers

Issue 11 • Date Nov 1988

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Displaying Results 1 - 25 of 26
  • Fault-tolerant matrix triangularizations on systolic arrays

    Publication Year: 1988, Page(s):1434 - 1438
    Cited by:  Papers (26)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (380 KB)

    Examines the checksum methods of Abraham et al. for LU decomposition on multiprocessor arrays. Their methods are efficient for detecting a transient error, but expensive for correcting it due to the need for a computation rollback. The authors show how to avoid the rollback by using matrix updating techniques, and they introduce new checksum methods for Gaussian elimination with pairwise ... View full abstract»

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  • On functional testing of array processors

    Publication Year: 1988, Page(s):1480 - 1484
    Cited by:  Papers (1)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (416 KB)

    This correspondence presents a new testing method for single instruction multiple data (SIMD) VLSI arrays. A new fault model is presented. Faults are defined at the functional level. A systematic test generation procedure is derived. Testing is performed by sequences of instructions. Two criteria are used. The first criterion establishes the external observability and controllability of the instru... View full abstract»

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  • Broadcast normalization in systolic design

    Publication Year: 1988, Page(s):1428 - 1434
    Cited by:  Papers (10)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (496 KB)

    When a sequential algorithm is directly mapped into an array of processing elements, quite likely data broadcasts are required and their source places vary during the computation. The authors introduce a normalization method to fix the positions of the broadcast sources so that the derived design can be further transformed by retimings into a systolic array. The method is fully illustrated in desi... View full abstract»

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  • Two-phase deadlock detection algorithm

    Publication Year: 1988, Page(s):1454 - 1458
    Cited by:  Papers (2)  |  Patents (2)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (448 KB)

    A deadlock detection algorithm utilizing a transaction-wait-for (TWF) graph is presented. It is a fully distributed algorithm which allows multiple outstanding requests. The proposed algorithm can achieve improved overall performance, using multiple disjoint controllers coupled with the two-phase property, while maintaining the simplicity of centralized schemes. The detection step is divided into ... View full abstract»

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  • A distributed algorithm for fault diagnosis in systems with soft failures

    Publication Year: 1988, Page(s):1476 - 1480
    Cited by:  Papers (3)  |  Patents (1)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (560 KB)

    The problem of diagnosis of soft failures at the system level in large and fully distributed networks of processors (or units) is considered. A system model in which each of the network's units is assumed to possess the ability to test (or evaluate) certain other units for the presence of failures is employed. Using this model and assuming that the total number of faulty units does not exceed a gi... View full abstract»

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  • Test pattern generation for API faults in RAM

    Publication Year: 1988, Page(s):1426 - 1428
    Cited by:  Papers (7)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (268 KB)

    The algorithm for detecting pattern-sensitive faults in memories, as presented by K.K. Salnja, K. Kinoshita (ibid., vol.34, no.3, p.284-7, 1985), is simplified. In addition, a new algorithm is presented which has a near optimal WRITE sequence View full abstract»

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  • Performance prediction and calibration for a class of multiprocessors

    Publication Year: 1988, Page(s):1353 - 1365
    Cited by:  Papers (29)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (1020 KB)

    A model for predicting multiprocessor performance on iterative algorithms is developed. Each iteration consists of some amount of access to global data and some amount of local processing. The iterations may be synchronous or asynchronous, and the processors may or may not incur waiting time, depending on the relationship between the access time and processing time. The effect on performance of th... View full abstract»

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  • The design of totally self-checking TMR fault-tolerant systems

    Publication Year: 1988, Page(s):1450 - 1454
    Cited by:  Papers (17)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (444 KB)

    A totally self-checking triple modular redundancy (TSC-TMR) system consists of a conventional TMR system monitored by a TSC circuit with two outputs indicating information errors and internal faults. The internal fault indication is independent of the output information errors and indicates masked errors of modular units or faults in the monitoring circuit itself. The information error indication ... View full abstract»

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  • Carry-free addition of recoded binary signed-digit numbers

    Publication Year: 1988, Page(s):1470 - 1476
    Cited by:  Papers (57)  |  Patents (1)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (644 KB)

    Signed-digital number representation systems have been defined for any radix r⩾3 with digit values ranging over the set {-α,···,-1,0,1,···, α}, where α is an arbitrary integer in the range r/2<α<r. Such number representation systems possess sufficient redundancy to allow for the annihilation of c... View full abstract»

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  • A systolic array for the assignment problem

    Publication Year: 1988, Page(s):1422 - 1425
    Cited by:  Papers (5)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (284 KB)

    A pure systolic realization of an algorithm for solving the n ×n assignment problem is presented. This systolic algorithm can be implemented on an homogeneous hexagonal processor array and requires O(n2) area complexity and O(n2) time complexity View full abstract»

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  • Performance analysis of multistage interconnection networks with hierarchical requesting model

    Publication Year: 1988, Page(s):1438 - 1442
    Cited by:  Papers (17)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (472 KB)

    Analyzes the performance of the multistage interconnection networks (MINs) for interconnecting N processors or N processors to N commonly shared memory modules in a multiprocessor system. A general model, called hierarchical requesting model, has been proposed. The performance of the MINs with respect to their memory bandwidth is analyzed and is compared to that of a cro... View full abstract»

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  • Connectivity of Imase and Itoh digraphs

    Publication Year: 1988, Page(s):1459 - 1461
    Cited by:  Papers (17)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (280 KB)

    An important problem in the design of efficient interconnection networks consists of finding digraphs with a minimal diameter for a given number of nodes n and a given degree d. The best family known at present, denoted by G(n,d), has been proposed by Imase and Itoh, ibid., vol.C-32, p.782-4 (1983). Its vertex set is the set of integers modulo ... View full abstract»

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  • Optimal chaining in expression trees

    Publication Year: 1988, Page(s):1366 - 1374
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (804 KB)

    Chaining is the ability to pipeline two or more vector instructions on Cray-1 like machines. The authors show how to optimally use this feature to compute (vector) expression trees in the context of automatic code generation. They present a linear time scheduling algorithm for finding an optimal order of evaluation for a machine with a bounded number of registers View full abstract»

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  • Accurate low-cost methods for performance evaluation of cache memory systems

    Publication Year: 1988, Page(s):1325 - 1336
    Cited by:  Papers (83)  |  Patents (4)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (944 KB)

    Trace-driven simulation is a simple way of evaluating cache memory systems with varying hardware parameters. But to evaluate realistic workloads, simulating even a few million addresses is not adequate and such large scale simulation is impractical from the consideration of space and time requirements. New methods of simulation based on statistical techniques are proposed for decreasing the need f... View full abstract»

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  • Relationship between P-valued majority functions and P -valued threshold functions

    Publication Year: 1988, Page(s):1442 - 1445
    Cited by:  Papers (5)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (316 KB)

    In a previous paper (Trans. IECE Japan, vol.J63-D, p.493-500, 1980, vol.J64-D, p.172-3, 1981 and vol.E-67, p.47-8, 1984), the authors defined a new class of multiple-valued logic functions, called multiple-valued majority functions. The authors clarifies the distinction of multiple-valued majority functions from multiple-valued threshold functions through the difference between a number function a... View full abstract»

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  • Binary decision tree test functions

    Publication Year: 1988, Page(s):1461 - 1465
    Cited by:  Papers (4)  |  Patents (3)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (432 KB)

    A class of multivariable logic functions which are suitable for use as binary decision tree node test functions is considered. These functions can be regarded as a natural extension of the polarity test normally used. The properties of these functions are discussed. A method for obtaining a reduced but not necessarily optimal tree is presented View full abstract»

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  • High-speed CAM-based architecture for a Prolog machine (ASCA)

    Publication Year: 1988, Page(s):1375 - 1383
    Cited by:  Papers (15)  |  Patents (1)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (768 KB)

    A content addressable memory (CAM)-based machine architecture is proposed for a high-speed Prolog machine. This Prolog machine attempts to speed up the total Prolog execution performance by using a hierarchical pipelined scheme and a CAM-based backtracking scheme. The hierarchical pipelined scheme reduces the total number of Prolog execution steps to half of that using the conventional method. The... View full abstract»

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  • The distribution of waiting times in clocked multistage interconnection networks

    Publication Year: 1988, Page(s):1337 - 1352
    Cited by:  Papers (52)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (940 KB)

    Analyzes the random delay experienced by a message traversing a buffered, multistage packet-switching banyan network. The authors find the generating function for the distribution of waiting time at the first stage of the network for a very general class of traffic, assuming messages have discrete sizes. For example, traffic can be uniform or nonuniform, messages can have different sizes, and mess... View full abstract»

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  • The extra stage Gamma network

    Publication Year: 1988, Page(s):1445 - 1450
    Cited by:  Papers (12)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (424 KB)

    The augmented data manipulator (ADM), inverse augmented data manipulator (IADM), and the gamma network are based on the plus-minus-2 i connection patterns. In such a network, there exists multiple paths to connect a source S to a destination D except when S=D. The number of paths for ( S,D) is a function of the tag value (D-... View full abstract»

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  • Transmission delays in hardware clock synchronization

    Publication Year: 1988, Page(s):1465 - 1467
    Cited by:  Papers (10)  |  Patents (5)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (288 KB)

    Various methods, both with software and hardware, have been proposed to synchronize a set of physical clocks in the system. Software methods are very flexible and economical but suffer an excessive time overhead, whereas hardware methods require no time overhead but are unable to handle transmission delays in clock signals. The effects of nonzero transmission delays in synchronization have been st... View full abstract»

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  • Heuristic algorithms for task assignment in distributed systems

    Publication Year: 1988, Page(s):1384 - 1397
    Cited by:  Papers (224)  |  Patents (5)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (1192 KB)

    Investigate the problem of static task assignment in distributed computing systems, i.e. given a set of k communicating tasks to be executed on a distributed system of n processors, to which processor should each task be assigned? The author proposes a family of heuristic algorithms for Stone's classic model of communicating tasks whose goal is the minimization of the total execu... View full abstract»

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  • A new class of fault-tolerant static interconnection networks

    Publication Year: 1988, Page(s):1468 - 1470
    Cited by:  Papers (2)  |  Patents (2)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (300 KB)

    The authors present a new class of interconnection networks using combinatorial block designs. These networks are highly structured and have strong fault-tolerant properties. They also have a free parameter that allows tradeoffs to be made between performance and cost in a fairly continuous way View full abstract»

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  • Interstitial redundancy: an area efficient fault tolerance scheme for large area VLSI processor arrays

    Publication Year: 1988, Page(s):1398 - 1410
    Cited by:  Papers (75)  |  Patents (6)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (1032 KB)

    In the proposed scheme, spare PEs are located at interstitial sites within the array. Each spare can functionally replace any one of the neighboring primary PEs that are connected to it. Because spares are physically close to the PE that they replace, restructured interconnections are short, minimizing performance degradation. This structure can incorporate different levels of redundancy depending... View full abstract»

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  • Comparative analysis of different implementations of multiple-input signature analyzers

    Publication Year: 1988, Page(s):1411 - 1414
    Cited by:  Papers (4)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (352 KB)

    Signature analysis is an accepted method of obtaining data compression for built-in testing applications. The author deals with a unified approach to the analysis of multiple-input signature analyzers by considering them as finite state switching circuits. This approach is used to investigate and compare different implementations, and it is shown that there is a large range of alternatives to achi... View full abstract»

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  • A multiple fault-tolerant processor network architecture for pipeline computing

    Publication Year: 1988, Page(s):1414 - 1418
    Cited by:  Papers (4)  |  Patents (1)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (440 KB)

    Certain fault-tolerant multiprocessor networks that can emulate linear array interconnections are considered. The system is fault tolerant of (m-1) node and link failures. One of the particularly attractive features of this network is that it allows for a linear array structure starting with any node even in spite of (m -2) faults. The configuration algorithm is fully distributed... View full abstract»

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The IEEE Transactions on Computers is a monthly publication with a wide distribution to researchers, developers, technical managers, and educators in the computer field.

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Editor-in-Chief
Paolo Montuschi
Politecnico di Torino
Dipartimento di Automatica e Informatica
Corso Duca degli Abruzzi 24 
10129 Torino - Italy
e-mail: pmo@computer.org