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IEEE Design & Test of Computers

Issue 4 • Dec. 1992

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Displaying Results 1 - 8 of 8
  • System specification with the SpecCharts language

    Publication Year: 1992, Page(s):6 - 13
    Cited by:  Papers (15)  |  Patents (6)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (779 KB)

    The SpecCharts language, which builds on VHDL to meet the unique requirements of system-level specification and design, is described. With an underlying model of behavioral hierarchy, SpecCharts modeling constructs enable designers to capture system specifications simply and precisely. SpecCharts constructs facilitate system-level design tasks by permitting high-level communication, maintaining in... View full abstract»

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  • A behavioral fault simulator for Ideal

    Publication Year: 1992, Page(s):14 - 21
    Cited by:  Papers (2)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (625 KB)

    A method of performing fault simulation at the behavioral level by propagating faults through behavioral hardware descriptions is presented. The method is accurate because it uses fault models only at the gate level. Since it does not duplicate computations at the behavioral level for each fault, it is, on the average, faster than existing methods. Examples in the Ideal hardware description langua... View full abstract»

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  • An efficient signature computation method

    Publication Year: 1992, Page(s):22 - 26
    Cited by:  Papers (8)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (775 KB)

    A signature generation algorithm for linear-feedback shift register (LFSR)-based compactors used in fault simulation of built-in self-test digital circuits is presented. The algorithm uses small- to medium-size lookup tables to generate signatures for internal as well as external exclusive-OR LFSRs of any length. The basic concept can be extended to general linear compactors. Algorithms that conve... View full abstract»

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  • Delay-fault diagnosis by critical-path tracing

    Publication Year: 1992, Page(s):27 - 32
    Cited by:  Papers (28)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (805 KB)

    A delay fault diagnosis process consisting of simulation of the fault-free circuit with a four-valued logic algebra and critical-path tracing from primary outputs to primary inputs is presented. An alternative to fault simulation, the method requires no delay-size-based fault models and considers only the fault-free circuit. A sensitivity analysis process for improving diagnosis accuracy is also p... View full abstract»

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  • A fast partitioning method for PLA-based FPGAs

    Publication Year: 1992, Page(s):34 - 39
    Cited by:  Papers (5)  |  Patents (3)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (554 KB)

    A method for automatic multipartitioning of a multiple-output logic function into the smallest number of subfunctions for mapping to fixed-size PLAs of a field-programmable gate array (FPGA) chip is described. A detailed example to demonstrate the procedure is presented. It is shown that, for this example, the method produced almost optimum partitions in a fast and efficient manner.<> View full abstract»

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  • Shortening the design cycle for programmable logic

    Publication Year: 1992, Page(s):40 - 50
    Cited by:  Papers (4)  |  Patents (12)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (1023 KB)

    X-BLOX, a software tool for mapping architecture-independent designs to field-programmable gate arrays (FPGAs), is described. X-BLOX synthesizes a delay- and area-efficient logic-level design from an input specification consisting of a network of generic modules. The tool automatically propagates partial data type specification, performs architecture-specific design optimization, and performs cont... View full abstract»

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  • An MPGA-like FPGA

    Publication Year: 1992, Page(s):51 - 60
    Cited by:  Papers (2)  |  Patents (2)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (969 KB)

    The CP20K series of field-programmable gate array (FPGA) chips is described. Consisting of an array of individual CMOS transistors and small logic elements linked via antifuse-programmable interconnections to form large functional blocks, the CP20K closely mimics the flexibility and capacity of a mask-programmable gate array (MPGA). It is shown that the chip's fine-grained architecture makes it ea... View full abstract»

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  • IEEE P1149.5 Module Test and Maintenance Bus

    Publication Year: 1992, Page(s):62 - 65
    Cited by:  Papers (3)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (347 KB)

    The objectives and intended uses of the proposed IEEE P1149.5 Module Test and Maintenance Bus standard are reviewed. Design-for-test features being used in component designs to aid in component, board, subsystem, and system test and maintenance are reviewed. The relationship of the IEEE P1149.5 MTM bus to other test buses is outlined, and the operation protocol is described. Extensions of the stan... View full abstract»

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This Periodical ceased production in 2012. The current retitled publication is IEEE Design & Test.

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Editor-in-Chief
Krishnendu Chakrabarty