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Semiconductor Manufacturing, IEEE Transactions on

Issue 1 • Date Feb. 2008

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Displaying Results 1 - 21 of 21
  • Table of contents

    Publication Year: 2008 , Page(s): C1 - C4
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  • IEEE Transactions on Semiconductor Manufacturing publication information

    Publication Year: 2008 , Page(s): C2
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  • Special Section on the International Symposium for Quality Electronic Design 2007 (ISQED 2007)

    Publication Year: 2008 , Page(s): 1 - 2
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  • VARIUS: A Model of Process Variation and Resulting Timing Errors for Microarchitects

    Publication Year: 2008 , Page(s): 3 - 13
    Cited by:  Papers (84)
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (2292 KB) |  | HTML iconHTML  

    Within-die parameter variation poses a major challenge to high-performance microprocessor design, negatively impacting a processor's frequency and leakage power. Addressing this problem, this paper proposes a microarchitecture-aware model for process variation-including both random and systematic effects. The model is specified using a small number of highly intuitive parameters. Using the variation model, this paper also proposes a framework to model timing errors caused by parameter variation. The model yields the failure rate of microarchitectural blocks as a function of clock frequency and the amount of variation. With the combination of the variation model and the error model, we have VARIUS, a comprehensive model that is capable of producing detailed statistics of timing errors as a function of different process parameters and operating conditions. We propose possible applications of VARIUS to microarchitectural research. View full abstract»

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  • A New Flexible Algorithm for Random Yield Improvement

    Publication Year: 2008 , Page(s): 14 - 21
    Cited by:  Papers (4)
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (955 KB) |  | HTML iconHTML  

    This paper presents a new and improved solution for random yield improvement at the post-routing stage. The proposed solution is better suited for current processes, where a clustering effect has been observed resulting in differing particle densities in the metal and empty regions of the chip. To account for this clustering effect, we introduce the concept of weighted critical area to serve as a proxy for random yield loss. A new algorithm for weighted critical area minimization is also introduced. The proposed optimization solution derives a weighted critical area based on the user-specified particle densities. It then uses this weighted critical area information to dynamically select the appropriate critical area reduction technique in each local region to guarantee a reduction of the weighted critical area in both the local region and the whole layer. This makes the algorithm flexible and readily applicable to different process lines. It consistently improves the random yield irrespective of the particle densities in the metal and empty regions of the chip. View full abstract»

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  • DOE-Based Extraction of CMP, Active and Via Fill Impact on Capacitances

    Publication Year: 2008 , Page(s): 22 - 32
    Cited by:  Papers (2)  |  Patents (1)
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (936 KB) |  | HTML iconHTML  

    Chemical-mechanical polishing (CMP), active and via fills have become indispensable aspects of semiconductor manufacturing. CMP fills are used to reduce metal thickness variations due to chemical-mechanical polishing. Via fills are used to improve neighboring via printability and reliability of low-k and ultra low-k dielectrics. Active region fills are used for STI CMP uniformity and stress optimization. Although modern parasitic extraction tools accurately handle grounded fills and regular interconnects, such tools use only rough approximations to assess the capacitance impact of floating fills, such as assuming that floating fills are grounded or that each fill is merged with neighboring ones. To reduce such inaccuracies, we provide a design of experiments (DOE) which complements what is possible with existing extraction tools. Through the proposed DOE set, a design or mask house can generate normalized fill tables to correct for the inaccuracies of existing extraction tools when floating fills are present. Golden interconnect capacitance values can be updated using these normalized fill tables. Our proposed DOE enables extensive analyses of fill impacts on coupling capacitances. We show through 3-D field solver simulations that the assumptions used in extractors result in significant inaccuracies. We present analyses of fill impacts for an example technology and also provide analyses using the normalized fill tables to be used in the extraction flow for three different standard fill algorithms. We also extend our analyses and methodology to via fills and active region fills, which have more recently been introduced into semiconductor design-manufacturing methodologies and for which sufficient understanding is still lacking. View full abstract»

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  • Design Considerations for PD/SOI SRAM: Impact of Gate Leakage and Threshold Voltage Variation

    Publication Year: 2008 , Page(s): 33 - 40
    Cited by:  Papers (6)  |  Patents (2)
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (1520 KB) |  | HTML iconHTML  

    We present a critical study of the impact of gate tunneling currents on the yield of 65-nm partially depleted/silicon-on-insulator (PD/SOI) SRAM designs. A new gate leakage monitor structure is developed to obtain device-specific gate leakage characteristics of the SRAM cells. This allows us to explore the design space accurately with reliable process information at an early stage. By relying on supply voltage-dependent analysis, it is shown that the gate-leakage impact on the cell yield can be nonmonotonic and substantial even for nondefective devices. It is also shown that design optimizations such as increased operating voltages or shorter hierarchical bitline architecture can help alleviate the gate-leakage impact on yield. Mixture importance sampling is used to estimate yield in terms of cell writability and stability. Threshold voltage variations to model random fluctuation effects are extrapolated from hardware results. View full abstract»

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  • Design-for-Manufacture for Multigate Oxide CMOS Process

    Publication Year: 2008 , Page(s): 41 - 45
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (1956 KB) |  | HTML iconHTML  

    Design-for-manufacture (DFM) for thick gate oxide layout in a dual gate oxide product is investigated. Careless placement and layout for thick gate oxide transistors in the multigate oxide chip can cause significant yield loss. The root cause of the yield loss is that the thick gate oxide can impact the uniformity of the adjacent thin gate oxide thickness. Further experiments' results show that the optimization of thick gate oxide transistor layout for the same product can improve the yield. Besides tweaking the gate oxide etching process to overcome the difficulty of multi oxide product manufacture, the guidelines for a good gate oxide layout practice are provided to facilitate the manufacture. View full abstract»

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  • Defect or Variation? Characterizing Standard Cell Behavior at 90 nm and Below

    Publication Year: 2008 , Page(s): 46 - 54
    Cited by:  Papers (8)
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (990 KB) |  | HTML iconHTML  

    Historically, design margin and defects have been viewed as different topics, one a part of design and the other a part of a test. Shrinking process geometries are making the two part of a continuum. This paper discusses the leakage and delay behavior associated with classic resistive defects and compares it with transistor variation due to lithography. View full abstract»

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  • Decomposition and Analysis of Process Variability Using Constrained Principal Component Analysis

    Publication Year: 2008 , Page(s): 55 - 62
    Cited by:  Papers (9)
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (1253 KB) |  | HTML iconHTML  

    Process-induced variability has become a predominant limiter of performance and yield of IC products especially in a deep submicron technology. However, it is difficult to accurately model systematic process variability due to the complicated and interrelated nature of physical mechanisms of variation. In this paper, a simple and practical method is presented to decompose process variability using statistics of the measurements from manufacturing inline test structures without assuming any underlying model for process variation. The decomposition method utilizes a variant of principal component analysis and is able to reveal systematic variation signatures existing on a die-to-die and wafer-to-wafer scale individually. Experimental results show that the most dominant die-to-die variation and wafer-to-wafer variation represent 31% and 25% of the total variance of a large set of manufacturing inline parameters in 65-nm SOI CMOS technology. The process variation in RF circuit performance is also analyzed and shown to contain 66% of process variation obtained with manufacturing inline parameters. View full abstract»

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  • Variation

    Publication Year: 2008 , Page(s): 63 - 71
    Cited by:  Papers (12)
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (2336 KB) |  | HTML iconHTML  

    Variation afflicts the design, manufacture, and operation of integrated circuits. Techniques and tools are needed in three areas to address variation: statistical metrology, advanced process control, and design for manufacturability. First, statistical metrology seeks to characterize and model variations and their sources. Advanced metrology helps to understand geometric and material property variations, while variation test structures and test circuits enable study of the impact of specific or aggregate variations on performance. Second, advanced process control attempts to reduce process variation through sensing and feedback/feedforward control during fabrication. Third, design for manufacturability (DFM) seeks methods to improve performance and yield given process and environmental variation, through robust design, increased regularity, and other approaches. Finally, linkages between these areas, particularly between statistical metrology and DFM, will be important and empowering. View full abstract»

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  • The Determination and Indetermination of Service Times in Manufacturing Systems

    Publication Year: 2008 , Page(s): 72 - 82
    Cited by:  Papers (8)
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (712 KB) |  | HTML iconHTML  

    The notion of service times is of such fundamental importance in the analysis of queues that it has long been taken for granted. Intuitively, it is used to represent the time interval that a server is capable of completing a dispatched job. However, actual measurements of service times under simple queues in production lines have encountered practical difficulties, in spite of its seemingly deterministic nature. Previous studies have introduced concepts of effective process times to quantify service times. Besides notions of theoretical processing times, raw process times and queueing times, among others, are commonly used in various applications. Their existence causes confusion in the determination of service times and clarification of such terminologies is needed. A simple model is examined to quantify the various concepts and establish their interrelationships. This paper brings out new properties of effective process times with a dynamic dependence on utilization. Discrete event simulations are conducted to verify these properties and explain the phenomenon of indetermination of service times. Both theoretical prediction and simulation results show that unless the system is fully loaded, service time and effective process time are not equivalent and it cannot be measured directly from observations of effective process times. View full abstract»

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  • A Multiagent-Based Decision-Making System for Semiconductor Wafer Fabrication With Hard Temporal Constraints

    Publication Year: 2008 , Page(s): 83 - 91
    Cited by:  Papers (15)
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (832 KB) |  | HTML iconHTML  

    This paper presents a decision-making system for semiconductor wafer fabrication facilities, or wafer fabs, with hard interoperation temporal constraints. The decision-making system is developed based on a multiagent architecture that is composed of scheduling agents, workcell agents, machine agents, and product agents. The decision-making problem is to allocate lots into each workcell to satisfy both logical and temporal constraints. A dynamic planning-based approach is adopted for the decision-making mechanism so that the dynamic behaviors of the wafer fab such as aperiodic lot arrivals and reconfiguration can be taken into consideration. The scheduling agents compute quasi-optimal schedules through a bidding mechanism with the workcell agents. The proposed decision-making mechanism uses a concept of temporal constraint sets to obtain a feasible schedule in polynomial steps. The computational complexity of the decision-making mechanism is proven to be, where is the number of operations of a lot and is the cardinality of the temporal constraint set. View full abstract»

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  • Evaluating Reliance Level of a Virtual Metrology System

    Publication Year: 2008 , Page(s): 92 - 103
    Cited by:  Papers (35)  |  Patents (2)
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (1086 KB) |  | HTML iconHTML  

    This paper proposes a novel method for evaluating the reliability of a virtual metrology system (VMS). The proposed method calculates a reliance index (RI) value between zero and one by analyzing the process data of production equipment to determine the reliability of the virtual metrology results. This method also defines an RI threshold. If an RI value exceeds the threshold, the conjecture result is reliable; otherwise, the conjecture result needs to be further examined. Besides the RI, the method also proposes process data similarity indexes (SIs). The SIs are defined to assess the degree of similarity between the input set of process data and those historical sets of process data used to establish the conjecture model. The proposed method includes two types of SIs: global similarity index (GSI) and individual similarity index (ISI). Both GSI and ISI are applied to assist the RI in gauging the reliance level and locating the key parameter(s) that cause major deviation, thus resolving the VMS manufacturability problem. An illustrative example involving 300-mm semiconductor foundry etching equipment is presented. Experimental results demonstrate that the proposed method is applicable to the VMS of production equipment (such as that for semiconductor and TFT-LCD). View full abstract»

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  • Investigation of Anomalous Inversion CV Characteristics for Long-Channel MOSFETs With Leaky Dielectrics: Mechanisms and Reconstruction

    Publication Year: 2008 , Page(s): 104 - 109
    Cited by:  Papers (1)
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (518 KB) |  | HTML iconHTML  

    This paper investigates anomalous inversion capacitance-voltage (C-V) attenuation for MOSFETs with leaky dielectrics. We propose to reconstruct the inversion C-V characteristic based on long-channel MOSFETs using the concept of intrinsic input resistance (Rii). The concept of Rii has been validated by segmented BSIM4/SPICE simulation. Our reconstructed C-V characteristics show poly-depletion effects, which are not visible in the two-frequency three-element method and agree well with the North Carolina State University-CVC simulation results. The intrinsic input resistance dominates the overall gate-current-induced debiasing effect (~95% for L = 20 mum) and can be extracted directly from the I-V characteristics. Due to its simplicity, our proposed Rii approach may provide an option for regular process monitoring purposes. View full abstract»

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  • Highly Manufacturable and Reliable HfSiON N-FET With Poly-Si/a-Si Stacked Gate for LSTP Applications

    Publication Year: 2008 , Page(s): 110 - 115
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (678 KB) |  | HTML iconHTML  

    We have proposed a novel poly-Si/a-Si/HfSiON transistor to enhance reliabilities without performance degradation for a 65-nm-node low standby power (LSTP) application. By insertion of a thin amorphous-Si layer between the Poly-Si gate electrode and HfSiON, both phosphorus penetration from gate electrode and a reaction at gate electrode/HfSiON interface are successfully suppressed, so that positive bias temperature instability, one of the biggest issues for high-k gate dielectric, is drastically improved by two orders of magnitude. By carefully optimizing the gate stack structure of HfSiON, the HfSiON device can satisfy both lower gate leakage and gate-induced drain leakage at the same time. As a result, an excellent Ion- Istandby (= Ig + loff) characteristic can be achieved, compared to the conventional SiON device. The a-Si insertion technique can realize the combination between the high-k gate dielectric and Poly-Si for future LSTP applications. View full abstract»

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  • Transient Thermoelastic Response of Nanofilms Under Radiation Heating From Pulsed Laser-Induced Plasma

    Publication Year: 2008 , Page(s): 116 - 122
    Cited by:  Papers (3)
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (835 KB) |  | HTML iconHTML  

    Measuring transient surface temperatures of substrates excited by nanosecond impulsive-type thermal sources is a nontrivial problem due to limited response times of many current sensors and the thinness of thermal skin at the nanosecond-time scale. An indirect transient surface temperature measurement technique for nanofilms subjected to a nanosecond dynamic loading is presented and demonstrated. The intensity profile calibrated based on the plasma radiation energy measurements is used as a boundary condition for finite-element analysis to estimate the transient surface temperature and the stress tensor induced in a 100-nm chromium film bonded to a quartz substrate due to the thermal radiation heating of the laser-induced plasma. The current approach is useful for predicting the damage threshold of nanofilms in laser-induced plasma (LIP) particle cleaning, as the direct and indirect transient temperature measurements currently available are unreliable for nanosecond impulsive thermal excitations. Particle cleaning techniques based on LIP have been under development for damage-free removal of sub-100-nm particles. The plasma core formed in this cleaning approach is a source of nanosecond-range impulsive radiation and subsequent thermomechanical excitation of the substrate and, consequently, possible substrate damage. The transient temperature measurements are used to estimate the peak surface temperature and the thermomechanical stresses induced in the substrate. View full abstract»

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  • Impact of Organic Contamination From Partially Fluorinated O-Ring in High-Temperature Nitride Process on DRAM Performance

    Publication Year: 2008 , Page(s): 123 - 126
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (1037 KB) |  | HTML iconHTML  

    This paper is concerned with organic contamination from a partially fluorinated o-ring used in a furnace for a high-temperature process. The organic outgas was confirmed by Fourier transform infrared analysis of the furnace exhaust gas. Experiments from practical trench dynamic random access memory disclosed that outgassed organic contaminants from the nitride process would severely worsen the tunneling leakage current performance of the storage dielectric and lead to fatal yield loss even though the cell capacitance was almost uninfluenced. To eliminate this yield detractor requires several test runs prior to real production after installation of the partially fluorinated o-ring; otherwise, a fully fluorinated o-ring is needed. From a cost viewpoint, the latter is highly suggested. View full abstract»

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  • 2008 IEEE International SOI Conference

    Publication Year: 2008 , Page(s): 127
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  • 2008 IEEE Compound Semiconductor IC Symposium

    Publication Year: 2008 , Page(s): 128
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    Freely Available from IEEE
  • IEEE Transactions on Semiconductor Manufacturing Information for authors

    Publication Year: 2008 , Page(s): C3
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Aims & Scope

The IEEE Transactions on Semiconductor Manufacturing addresses the challenging problems of manufacturing complex microelectronic components.

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Meet Our Editors

Editor-in-Chief

Anthony Muscat
Department of Chemical and Environmental Engineering
Harshbarger Bldg., Room 134
1133 E. James Rogers Way
University of Arizona
Tucson, AZ  85721