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Electron Devices, IEEE Transactions on

Issue 2 • Date Feb. 2008

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Displaying Results 1 - 25 of 41
  • Table of contents

    Publication Year: 2008 , Page(s): C1 - C4
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    Freely Available from IEEE
  • IEEE Transactions on Electron Devices publication information

    Publication Year: 2008 , Page(s): C2
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    Freely Available from IEEE
  • WEB-based Manuscript Processing

    Publication Year: 2008 , Page(s): 477
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  • Channel Temperature Determination in High-Power AlGaN/GaN HFETs Using Electrical Methods and Raman Spectroscopy

    Publication Year: 2008 , Page(s): 478 - 482
    Cited by:  Papers (26)
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (330 KB) |  | HTML iconHTML  

    Self-heating in AlGaN/GaN HFETs was investigated using electrical analysis and micro-Raman thermography. Two typically employed electrical methods were assessed to provide a simple means of extracting average channel temperatures in devices. To quantify the accuracy of these electrical temperature measurements, micro-Raman thermography was used to provide submicron resolution temperature information in the source-drain opening of the devices. We find that electrical methods significantly underestimate peak channel temperatures, due to the fact that electrical techniques measure an average temperature over the entire active device area. These results show that, although electrical techniques can be used to provide qualitative comparisons between different devices, they have challenges for the accurate estimation of peak channel temperatures. This needs to be taken into account for lifetime testing and reliability studies based on electrical temperature measurements. View full abstract»

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  • Polarization Engineering on Buffer Layer in GaN-Based Heterojunction FETs

    Publication Year: 2008 , Page(s): 483 - 488
    Cited by:  Papers (6)
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (325 KB) |  | HTML iconHTML  

    To improve the pinched-off characteristics of an AlGaN/GaN heterojunction field effect transistor (HJFET), the conduction band potential of an incorporated ALxGa1-xN buffer is designed to be upwardly convex in a band diagram. This approach utilizes the polarization effects specific to GaN-based materials by lowering the Al content x from 30% to 5% almost linearly toward the front side. Fabricated field effect transistors (FETs) adopting the designed buffer have demonstrated the following advanced characteristics in comparison to those of a FET adopting a conventional GaN buffer: less than one-tenth of the buffer leakage current, a gate-to-drain breakdown voltage BVgd twice or more as high, and remarkably improved carrier confinement and pinched-off behavior. The FETs are operated in an enhancement mode with a gate-to-channel distance thick enough to prevent tunneling current through the gate. View full abstract»

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  • Stability and 2-D Simulation Studies of Avalanche Breakdown in 4H-SiC DMOSFETs With JTE

    Publication Year: 2008 , Page(s): 489 - 494
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (431 KB) |  | HTML iconHTML  

    In this paper, the stability of n-channel 4H-silicon carbide (SiC) DMOSFETs with junction termination extension (JTE) was assessed by measuring the breakdown voltage (BV) of these devices before and after bias stress at a high temperature. The BV slumped after the DMOSFET was bias stressed at 1200 V for 2 h at 175degC, and the slumped BV dynamically recovered to the prestress value during the poststress period. Computer simulation suggests that the BV slump and its recovery are dominated by the positive charge trapping/detrapping phenomena at the SiC/fleld oxide interface in the JTE structure, rather than the trapping/detrapping at the SiC/gate oxide interface in the cell structure. A positive interface charge of approximately one-third of the sheet dopant concentration of the JTE region, lowers BV by 150 V, which is the typical measured BV slump of the DMOSFETs of this paper. View full abstract»

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  • Double-Recessed High-Frequency AlInGaN/InGaN/GaN Metal–Oxide Double Heterostructure Field-Effect Transistors

    Publication Year: 2008 , Page(s): 495 - 499
    Cited by:  Papers (2)
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (271 KB) |  | HTML iconHTML  

    We demonstrate a low-threshold AlInGaN/InGaN/GaN metal-oxide semiconductor double heterostructure field-effect transistor (MOS-DHFET) for high-frequency operation. A combination of an InGaN channel (for carrier confinement), a DRE process, and a new digital-oxide-deposition technique helped us to achieve MOS-DHFET devices with extremely low subthreshold leakage currents. This reduction in output conductance (short channel effect) resulted in a high cutoff gain frequency fT of about 65 GHz and a current gain frequency f max of 94 GHz. The devices exhibited high drain-currents of 1.3 A/mm and delivered RF powers of 3.1 W/mm at 26 GHz with a 35 V drain bias. View full abstract»

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  • A 6,13-bis(Triisopropylsilylethynyl) Pentacene Thin-Film Transistor Using a Spun-On Inorganic Gate-Dielectric

    Publication Year: 2008 , Page(s): 500 - 505
    Cited by:  Papers (11)
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (607 KB) |  | HTML iconHTML  

    We present the latest results of the use of soluble materials such as organic semiconductors (OSCs) or gate-dielectrics for simplified processing of organic thin-film transistors (OTFTs). In this paper, we described our fabrication of a solution-processed OTFT with 6,13-bis(triisopropylsilylethynyl) pentacene (TIPS-pentacene) as the OSC and siloxane-based spin-on glass (SOG) as the inorganic gate-dielectric. Also, synthesized TIPS-pentacene and SOG were examined for use as the OSC and gate-dielectric in an OTFT. From electrical measurements, we obtained device performance characteristics such as charge carrier mobility, threshold voltage, current ON/OFF ratio, and subthreshold swing, which were 6.48 times 10-3 cm2/V ldr s, -13 V, ~100, and 1.83 V/dec, respectively. View full abstract»

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  • Modeling of Programming and Read Performance in Phase-Change Memories—Part I: Cell Optimization and Scaling

    Publication Year: 2008 , Page(s): 506 - 514
    Cited by:  Papers (45)  |  Patents (3)
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (804 KB) |  | HTML iconHTML  

    One of the major concerns for the feasibility of phase-change memories is the reduction of the programming current. To this aim, several efforts have been dedicated both on cell geometry and on material engineering. This paper addresses programming-current minimization by the optimization of the cell geometry and materials, programming-current scaling, and the tradeoff between programming and readout performances of the cell. A general procedure to find the optimum-cell geometry is proposed and applied to a prototype vertical cell. Then, the evolution of program and read performances through technology nodes is analyzed by numerical simulations with the aid of an analytical model, for both the isotropic- and nonisotropic-scaling approaches. The two scaling approaches are discussed and compared in terms of program and read cell performances. Finally, material optimization is considered for further program-read improvement. View full abstract»

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  • Modeling of Programming and Read Performance in Phase-Change Memories—Part II: Program Disturb and Mixed-Scaling Approach

    Publication Year: 2008 , Page(s): 515 - 522
    Cited by:  Papers (13)  |  Patents (2)
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (732 KB) |  | HTML iconHTML  

    The scaling analysis of phase-change memory (PCM) cells is an essential step toward validation as a competitive technology in terms of array density and current consumption. While the current scaling has been addressed in a companion paper, we focus here on the thermal crosstalk, namely, the temperature increase in 1 bit in the array while an adjacent cell is being programmed by a high-current reset pulse. This parasitic heating may lead to partial crystallization in the amorphous phase and to a consequent resistance decrease after cycling. Our analysis shows that the thermal crosstalk strongly depends on the scaling approach used, e.g., isotropic or nonisotropic scaling. A new mixed-scaling option for PCM cells is proposed, which provides the maximum decrease of programming current compatible with the reliability requirements deriving from the thermal crosstalk. The effects of this new scaling approach on the programmed volume and data retention are finally addressed. View full abstract»

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  • GaN Light-Emitting Diode with Deep-Angled Mesa Sidewalls for Enhanced Light Emission in the Surface-Normal Direction

    Publication Year: 2008 , Page(s): 523 - 526
    Cited by:  Papers (3)
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (327 KB) |  | HTML iconHTML  

    We have fabricated and characterized GaN LED devices whose mesa sidewalls are intentionally made deep and angled. The angled sidewalls efficiently deflect the photons guided laterally along the GaN epitaxial (epi) layer to a direction normal to the surface via total internal reflection. Regardless of the sidewall angle, the sidewall-deflector-integrated (SDI) LEDs exhibit significant enhancement in the light output from the device surface. The largest enhancement, which occurs when the mesa sidewall angle is about 30deg, is greater than 2times. Computer simulations based on ray optics correctly reproduce the sidewall angle dependence of the enhancement factor. Near-field emission patterns as well as space-resolved electroluminescence spectra also support that the enhancement in the light output is due to those additional photons that are guided laterally and deflected by the angled mesa sidewalls. View full abstract»

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  • An Organic Active-Matrix Imager

    Publication Year: 2008 , Page(s): 527 - 532
    Cited by:  Papers (20)
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (453 KB) |  | HTML iconHTML  

    In this paper, a proof of concept 4 x 4 active-matrix imager fabricated at near room temperature (< 95 degC) is presented. Conventional photolithography and inkjet printing were used to pattern integrated organic FETs and photoconductors. The design and characterization of a pixel circuit is described. A simple first-order calibration technique is used to partially compensate for fixed pattern noise. Following the calibration, the imager is shown to correctly image a "T" pattern. View full abstract»

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  • Design Constraints on FSC LCD

    Publication Year: 2008 , Page(s): 533 - 539
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (274 KB) |  | HTML iconHTML  

    Design constraints on field-sequential color liquid crystal displays (LCDs) are proposed and compared with those of conventional color filter LCDs. Application of these constraints to the design of LCD screens is demonstrated. View full abstract»

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  • High-Reliable and High-Speed 1.3 μm Complex-Coupled Distributed Feedback Buried-Heterostructure Laser Diodes With Fe-Doped InGaAsP/InP Hybrid Grating Layers Grown by MOCVD

    Publication Year: 2008 , Page(s): 540 - 546
    Cited by:  Papers (3)
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (577 KB) |  | HTML iconHTML  

    In this paper, we report the fabrication of high-reliability and high-speed 1.3 mum complex-coupled distributed feedback (CC-DFB) buried heterostructure (BH) laser diodes (LDs) with Fe-doped InGaAsP/InP hybrid grating layers. High optical coupling coefficient and eminent current confining ability are accomplished by combining the Fe-doped InGaAsP/InP current-blocking-grating (CBG) layers to provide both the distributed-feedback index-and gain-coupling coefficients. Besides, the narrow-stripe BH LDs are implemented by burying the active region with a Fe-doped InP current-blocking layer during the epitaxial regrowth. The fabricated CBG CC-DFB BH LDs at 20degC shows a low threshold current of 5.3 mA, a maximum light output power of 36 mW at 100 mA, a high slope efficiency of 0.41 mW/mA, and a side-mode suppression ratio (SMSR) of 42 dB at twice the threshold. In addition, these LDs exhibit a maximum operation temperature of 125degC, an extremely low threshold current of 15.8 mA at 90degC, a small variation in slope efficient of only -1 dB in the temperature range from 20degC to 80degC, and a characteristic temperature of 77 K and 56 K between 20 degC and 60degC, and 70degC and 120degC, respectively. Furthermore, these 1.3 mum CBG CC-DFB BH LDs exhibit a high-speed characteristic up to 11.8 GHz at room temperature and an estimated median lifetime of more than 1.1 times 105 h or 12.5 years at 5 mW and 85degC. View full abstract»

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  • On the Correct Extraction of Interface Trap Density of MOS Devices With High-Mobility Semiconductor Substrates

    Publication Year: 2008 , Page(s): 547 - 556
    Cited by:  Papers (135)  |  Patents (3)
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (481 KB) |  | HTML iconHTML  

    ldquoConventionalrdquo techniques and related capacitance-voltage characteristic interpretation were established to evaluate interface trap density on Si substrates. We show that blindly applying these techniques on alternative substrates can lead to incorrect conclusions. It is possible to both under- and overestimate the interface trap density by more than an order of magnitude. Pitfalls jeopardizing capacitance-and conductance-voltage characteristic interpretation for alternative semiconductor MOS are elaborated. We show how the conductance method, the most reliable and widely used interface trap density extraction method for Si, can be adapted and made reliable for alternative semiconductors while maintaining its simplicity. View full abstract»

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  • A Closed-Form Model for Thermionic Trap-Assisted Tunneling

    Publication Year: 2008 , Page(s): 557 - 564
    Cited by:  Papers (4)
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (245 KB) |  | HTML iconHTML  

    Recently, we proposed a trap-assisted tunneling model (2006) that includes tunneling of thermally activated electrons above the metal Fermi level for explaining the temperature-dependent leakage current in some semiconductor devices. In the present paper, we develop a closed-form version of this model, which provides physical insight by revealing the peak, energy location and spread of emitted electron distribution. The model also yields characteristic field parameters to identify the thermally activated regime of current versus field behavior and the location of peak emission. The closed-form solution of a complicated equation has been achieved using a geometrical interpretation of the integration operation, and by bisecting the range of trap energies, adopting separate approximations for the bisected segments, and then mathematically combining the two segments into a single continuous function valid for the entire range of trap energies. The closed-form model calculations match well with numerical integration results. View full abstract»

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  • A “Probe-Lift” MOS-Capacitor Technique for Measuring Very Low Oxide Leakage Currents and Their Effect on Generation Lifetime Extraction

    Publication Year: 2008 , Page(s): 565 - 571
    Cited by:  Papers (2)
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (642 KB) |  | HTML iconHTML  

    A new method for precisely measuring low gate oxide currents by measuring the charge leaking through the oxide in a pulsed metal oxide semiconductor capacitor (MOS-C) is presented. Using basic equipment, it is possible to measure currents less than 10 fA/cm2 . The relevant theory is developed to use these capacitance-time data to extract an approximate leakage current and the effect on the extracted generation lifetime. The technique is simple and requires the same equipment used for pulsed MOS-C generation lifetime measurements. Experimental results are presented, which are consistent with theory. View full abstract»

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  • The Effects of Mechanical Uniaxial Stress on Junction Leakage in Nanoscale CMOSFETs

    Publication Year: 2008 , Page(s): 572 - 577
    Cited by:  Papers (13)
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (318 KB) |  | HTML iconHTML  

    This paper reports the influences of uniaxial mechanical stress on the reverse-biased source/drain to substrate junction leakage of state-of-the-art 65 nm CMOS transistors. For n-channel metal-oxide-semiconductor (NMOS) transistors, the band-to-band tunneling (BTBT) dominates the junction leakage current due to heavily doped junction and pocket implants. However, for p-channel metal-oxide-semiconductor (PMOS) transistors with embedded SiGe source/drain, the leakage current is found to result from both BTBT and generation current due to defects generated in the SiGe layer and at the SiGe/Si interface. A four-point bending technique is used to apply mechanical uniaxial stress on NMOS and PMOS devices along the longitudinal direction. It was found that the leakage current of both devices increases (decreases) with applied uniaxial compressive (tensile) stress, and that the strain sensitivity of the junction leakage of NMOS transistors is much weaker than that of PMOS transistors. By combining the bending technique with process strained Si (PSS) technology, additional stress was applied to NMOS and PMOS with high built-in stress to investigate the characteristics of junction leakage under extremely high uniaxial stress. It is shown that uniaxial tensile stress can both enhance the NMOS device performance and decrease the junction leakage. However, for the PMOS, there exists a tradeoff between boosting the transistor performance and decreasing the junction leakage current, so there is a limit in the amount of compressive stress that can be beneficially applied. View full abstract»

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  • Scalable 3-D Fin-Like Poly-Si TFT and Its Nonvolatile Memory Application

    Publication Year: 2008 , Page(s): 578 - 584
    Cited by:  Papers (21)
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (422 KB) |  | HTML iconHTML  

    In this paper, we extensively investigated the structure and electrical characteristics of an n-type poly-Si thin-film transistor with a novel 3D fin-like channel. Further, owing to the high-quality thin film in the channel, an experimental device with a nonvolatile (NV) memory structure for system integration on panel or embedded memory applications is successfully demonstrated for the first time. By following the previously reported method and by improving the process conditions, the final fin-like channel shows a real 3D profile and a maximum aspect ratio of 3.5:1 with a minimum average width equal to 135 nm after an excimer laser annealing on a unique prepatterned amorphous silicon channel. The high-level dc characteristics, such as carrier's field-effect mobility up to 289 cm2 /V.s, subthreshold slope below 190 mV/dec, ON-OFF current ratio greater than 5 x 106, etc., reveal the effect of film quality and the advantage of the gate-all-around structure on the device's performance; moreover, it also indicates one potential scaling method for this technology. By applying a special program/erase (P/E) mode with electron injection/expulsion from the backside gate electrode, the NV memory structure in this channel demonstrates reasonable P/E characteristics, threshold voltage shifting of 1.41 V at | Vg = 12 V, pulse time = 1 ms, and acceptable reliability. View full abstract»

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  • Electrical Behavior and Technology Optimization of Si/SiGeC HBTs on Thin-Film SOI

    Publication Year: 2008 , Page(s): 585 - 593
    Cited by:  Papers (8)
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (1059 KB) |  | HTML iconHTML  

    A growing interest has been focused on silicon on insulator (SOI) technologies over the past years. Yet, few studies were carried out regarding the integration of vertical SiGe heterojunction bipolar transistors (HBTs) using such substrates. This paper deals both with the integration of a SiGeC HBT on thin-film CMOS-compatible SOI, and a comprehensive study of its electrical behavior based on physical simulation and electrical characterization. Various aspects of the optimization of device performances are described, considering process or layout improvements. View full abstract»

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  • Dynamic Power Model of CMOS Gates Driving Transmission Lines Based on Fourier Analysis

    Publication Year: 2008 , Page(s): 594 - 600
    Cited by:  Papers (1)
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (195 KB) |  | HTML iconHTML  

    This paper presents an analytical dynamic power model of CMOS gates driving transmission lines with distributed RLC parameters. It is shown that at high signal frequency, where the output voltage at the termination of a transmission line may not reach the steady state during a signal period, the charge and voltage at the end of the period become the initial conditions of the following periods and have a significant effect on dynamic power consumption. The proposed model takes these initial conditions into account, since it is based on Fourier series analysis. In this model, the dynamic power consumption is approximated by the summation of the first several Fourier-series-based terms. The accuracy of the model increases with the number of series terms, and arbitrary accuracy can be obtained by including appropriate number of the terms in the model. The model is much faster than simulation program with integrated circuit emphasis (SPICE), and its computational complexity is linear with the number of terms included. The model is also extended to CMOS gates driving distributed RLC trees and coupled multiconductor transmission lines. View full abstract»

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  • Subharmonically Pumped RF CMOS Paramps

    Publication Year: 2008 , Page(s): 601 - 608
    Cited by:  Papers (5)
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (431 KB) |  | HTML iconHTML  

    This paper discusses MOS-based RF integrated parametric amplifiers and converters (paramps). Specifically, MOS varactor characteristics are exploited to support subharmonically pumped configurations. Such configurations require lower frequency pumping, and thus, are more accommodating to CMOS pumps for millimeter-wave applications. Closed-form expressions are derived for the optimally biased accumulation-mode MOS varactor elastance based on pumping voltage, channel doping, and gate oxide thickness. Simple design equations for the pumped figure of merit, a metric common to all small-signal paramps, are obtained, resulting in a compact means of predicting integrated circuit performance. A comparison is made between MOS-based and diode-based designs (traditional and subharmonic) for a downconverting paramp topology. The importance of deep-depletion behavior is discussed. View full abstract»

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  • Device Design and Optimization Considerations for Bulk FinFETs

    Publication Year: 2008 , Page(s): 609 - 615
    Cited by:  Papers (10)
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (327 KB) |  | HTML iconHTML  

    Fabrication of FinFETs using bulk CMOS instead of silicon on insulator (SOI) technology is of utmost interest as it reduces the process costs. Using well-calibrated device models and 3-D mixed mode simulations, we show that bulk FinFETs can be optimized with identical performances as that of SOI FinFETs. Optimized bulk FinFETs are compared with the corresponding SOI FinFETs for a range of technology nodes using an extensive simulation and design methodology. Further, we extend the concept of body doping in bulk FinFETs to the case of lightly doped fins unlike the heavily doped fin cases reported earlier. The optimum body doping required for bulk FinFETs, and its multiple advantages are also systematically evaluated. We also show that device parasitics play a crucial role in the optimization of nanoscale bulk FinFETs. View full abstract»

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  • Rigorous Surface-Potential Solution for Undoped Symmetric Double-Gate MOSFETs Considering Both Electrons and Holes at Quasi NonEquilibrium

    Publication Year: 2008 , Page(s): 616 - 623
    Cited by:  Papers (15)
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (640 KB) |  | HTML iconHTML  

    This paper presents a rigorously-derived analytical solution of the Poisson equation with both electrons and holes in pure silicon, which is applied to the analysis of undoped symmetric double-gate transistors. An implicit surface-potential equation is obtained that can be solved by a second-order Newton-Raphson technique along with an appropriate initial guess. Within the assumption of holes at equilibrium that is being used in the existing literature, the new results, when compared with the models based on one carrier, reveal that missing the other carrier in the formulation results in a singularity in the gate capacitance exactly at flatband, which may give trouble for high-frequency analysis, although the errors in surface potentials are below the nano-volt range for all gate voltages. However, the solution without assuming constant hole imref, as presented in this paper for the first time, further pinpoints the inadequacy in existing theories of surface-potential solutions in double-gate MOSFETs with undoped thin bodies, although its application to transport solutions of terminal current/charge models depends highly on the type of source/drain structures and contacts. View full abstract»

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  • A Compact Model Satisfying Gummel Symmetry in Higher Order Derivatives and Applicable to Asymmetric MOSFETs

    Publication Year: 2008 , Page(s): 624 - 631
    Cited by:  Papers (9)
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (935 KB) |  | HTML iconHTML  

    This paper presents a new concept for the MOSFET saturation voltages at the drain and source sides referenced to bulk, and applies them to the popularly used smoothing functions for the effective drain-source voltage (Vds,eff ). The proposed model not only builds in physically all the terminal-bias variations, but is also extended to include source/drain asymmetry in real devices in a single-core compact model. The new model resolves a key bottleneck in existing models for passing the Gummel symmetry test (GST) in higher order derivatives, which has to be traded off for the geometry-dependent Vds,eff smoothing parameter. The complete drain-current model, including the effects of velocity saturation and overshoot as well as source/drain series resistance, has also been reformulated with the same ldquobulk-referencingrdquo concept. It is shown that the proposed model passes the GST in all higher order derivatives without any constraint on the value of the smoothing parameter. It also demonstrates potential extension to modeling asymmetric MOSFETs, which is becoming an important model capability. View full abstract»

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Aims & Scope

IEEE Transactions on Electron Devices publishes original and significant contributions relating to the theory, modeling, design, performance and reliability of electron and ion integrated circuit devices and interconnects.

 

Full Aims & Scope

Meet Our Editors

Acting Editor-in-Chief

Dr. Paul K.-L. Yu

Dept. ECE
University of California San Diego