Computers & Digital Techniques, IET
Issue 1 • Date January 2008
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Displaying Results 1 - 9 of 9
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Efficient residue number system iterative modular multiplication algorithm for fast modular exponentiation
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PDF (105 KB)
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FPGA accelerated multipliers over binary composite fields constructed via low hamming weight irreducible polynomials
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PDF (122 KB)
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Decision heuristic for Davis Putnam, Loveland and Logemann algorithm satisfiability solving based on cube subtraction
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PDF (204 KB)
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Critical race-free low-power nand match line content addressable memory tagged cache memory
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PDF (491 KB)
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Binary LNS-based naive Bayes inference engine for spam control: noise analysis and FPGA implementation
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PDF (229 KB)
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Design of simulation and analytical models for a 2D-meshed asymmetric adaptive router
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PDF (1068 KB)
