# IEEE Transactions on Circuits and Systems II: Express Briefs

## Filter Results

Displaying Results 1 - 25 of 26

Publication Year: 2008, Page(s): C1
| PDF (40 KB)
• ### IEEE Transactions on Circuits and Systems—II: Express Briefs publication information

Publication Year: 2008, Page(s): C2
| PDF (36 KB)
• ### Design Procedure for Settling Time Minimization in Three-Stage Nested-Miller Amplifiers

Publication Year: 2008, Page(s):1 - 5
Cited by:  Papers (23)
| | PDF (216 KB) | HTML

Low-power, low-voltage, and high-performance requirements are badly needed for operational amplifiers (op-amps) in modern applications. In this brief, a design method for minimizing the settling time in three-stage nested-Miller schemes is presented. As an application example, a CMOS 0.35-mum voltage follower with 115-dB dc gain and fastest step response to 1% accuracy level, is designed. Circuita... View full abstract»

• ### Delta–Sigma D/A Converter Using Binary- Weighted Digital-to-Analog Differentiator for Second-Order Mismatch Shaping

Publication Year: 2008, Page(s):6 - 10
Cited by:  Papers (3)
| | PDF (863 KB) | HTML

A multibit digital-analog (D/A) differentiator is used in the forward correction path of a dual-truncation delta-sigma (DeltaSigma) D/A converter (DAC) to obtain the desired second-order noise-shaping function for converting mismatch-induced in-band quantization noise to out-of-band frequencies. The multibit D/A differentiator can be configured by embedding binary-weighted current-steering DAC ele... View full abstract»

• ### A New CMOS Active Transformer QPSK Modulator With Optimal Bandwidth Control

Publication Year: 2008, Page(s):11 - 15
Cited by:  Papers (6)
| | PDF (462 KB) | HTML

This brief presents a new quadrature phase-shift keying (QPSK) modulator for Bluetooth applications with an optimal transaction bandwidth control. The modulator reduces the bandwidth of the modulated carrier by minimizing their transition sharpness. CMOS active transformers are developed and utilized in quadrature oscillator and multiplexer of the modulator to provide comparable phase noise perfor... View full abstract»

• ### Power-Aware Design of Nanometer MCML Tapered Buffers

Publication Year: 2008, Page(s):16 - 20
Cited by:  Papers (7)
| | PDF (283 KB) | HTML

A strategy to design MOS current-mode logic (MCML) tapered buffers is discussed. Closed-form expressions of the speed and the power consumption of MCML tapered buffers are first derived. Then, analytical criteria are presented to explore the power-delay design space and properly size the number of stages and the current tapering factor under a speed/power constraint. These criteria incorporate dee... View full abstract»

• ### Multiple Threshold Voltage Design Scheme for CMOS Tapered Buffers

Publication Year: 2008, Page(s):21 - 25
Cited by:  Papers (12)
| | PDF (947 KB) | HTML

This brief proposes lower power lower delay design for CMOS tapered buffers. A slight increase in the threshold voltage is shown to have an exponential effect in reducing the total power dissipation. The corresponding increase in the propagation delay is compensated for by increasing the number of buffer stages such that there is still an overall significant reduction in the total power dissipatio... View full abstract»

• ### Effective Capacitance of Inductive Interconnects for Short-Circuit Power Analysis

Publication Year: 2008, Page(s):26 - 30
Cited by:  Papers (4)
| | PDF (264 KB) | HTML

Interconnect resistance and inductance shield part of the load capacitance, resulting in a faster voltage transition at the output of the driver. Ignoring this shielding effect may induce significant error when estimating short-circuit power. In order to capture this shielding effect, an effective capacitance of a distributed RLC load is presented for accurately estimating the short-circuit power.... View full abstract»

• ### A Timing-Driven Approach to Synthesize Fast Barrel Shifters

Publication Year: 2008, Page(s):31 - 35
Cited by:  Papers (4)
| | PDF (225 KB) | HTML

In modern digital signal processing and graphics applications, the shifter is an important module, consuming a significant amount of delay. This brief presents an architectural optimization approach to synthesize a faster barrel shifter block, which can be useful to reduce the delay of the design without significantly increasing the area. We have divided the problem of generating the shifter into ... View full abstract»

• ### Random Walk Guided Decap Embedding for Power/Ground Network Optimization

Publication Year: 2008, Page(s):36 - 40
| | PDF (527 KB) | HTML

The reliability of power/ground networks is becoming significantly important in modern integrated circuits, while decap insertion is a main approach to enhance the power grid safety. In this brief, we propose a fast and efficient decap allocation algorithm, and adequately consider the leakage effect of decap. This approach borrows the idea of random walks to perform circuit partitioning and does s... View full abstract»

• ### A Signomial Programming Approach for Binary Image Restoration by Penalized Least Squares

Publication Year: 2008, Page(s):41 - 45
Cited by:  Papers (7)
| | PDF (305 KB) | HTML

The authors present a novel optimization approach, using signomial programming (SP), to restore noise-corrupted binary and grayscale images. The approach requires the minimization of a penalized least squares functional over binary variables, which has led to the design of various approximation methods in the past. In this brief, we minimize the functional as a SP problem which is then converted i... View full abstract»

• ### On the Absence of Limit Cycles in State-Space Digital Filters With Minimum L2-Sensitivity

Publication Year: 2008, Page(s):46 - 50
Cited by:  Papers (13)
| | PDF (333 KB) | HTML

This brief proposes a systematic approach to synthesis of limit cycle free state-space digital filters with minimum L2-sensitivity. We synthesize the minimum L2-sensitivity realization adopting the balanced realization as an initial realization. The coordinate transformation matrix which transforms the balanced realization into the minimum L2-sensitivity realizatio... View full abstract»

• ### Integrated Phase-Locking Scheme for SDFT-Based Harmonic Analysis of Periodic Signals

Publication Year: 2008, Page(s):51 - 55
Cited by:  Papers (21)
| | PDF (246 KB) | HTML

The sliding discrete Fourier transform splits periodic signals into selected harmonic components, as on-line time functions. Ordinarily, the sampling frequency is equal to the product of the nominal signal frequency and the window width N. However, when the signal frequency drifts, to avoid the phase and magnitude errors, the sampling frequency can be adaptively adjusted using the phase-error itse... View full abstract»

• ### Analytic Expressions of Two Discrete Hermite–Gauss Signals

Publication Year: 2008, Page(s):56 - 60
Cited by:  Papers (3)
| | PDF (166 KB) | HTML

This brief presents the analytical expressions for the discrete zeroth-and first-order Hermite-Gauss functions, which are normally obtained by numerical methods. These two ldquoGaussian-typerdquo functions have the following interesting properties. (a) They have simple analytic forms (form of a product) when the lengths of the functions satisfy certain conditions. (b) They are the eigenvectors of ... View full abstract»

• ### Remarks on $n$ -D Polynomial Matrix Factorization Problems

Publication Year: 2008, Page(s):61 - 64
Cited by:  Papers (6)
| | PDF (136 KB) | HTML

Multidimensional (n-D) polynomial matrix factorizations are intimately linked to many problems of multidimensional systems and signal processing. This paper gives a new result for a n-D polynomial matrix to have an minor prime factorization using methods from computer algebra. This result may be regarded as a generalization of a previous criterion under a special restriction [IEEE Trans. Circuits ... View full abstract»

• ### Attack Vulnerability of Complex Communication Networks

Publication Year: 2008, Page(s):65 - 69
Cited by:  Papers (34)
| | PDF (144 KB) | HTML

The Internet has been studied as a typical example of real-world complex networks. In this brief, we study the traffic performance of the Internet when it encounters a random or intentional attack. Different from previous approaches, the congestion control protocols are considered so that the bandwidth can be reallocated among flows. In this way, cascading breakdown is less likely to happen. The f... View full abstract»

• ### $L(j, , k)$-Labelings of Kronecker Products of Complete Graphs

Publication Year: 2008, Page(s):70 - 73
Cited by:  Papers (8)
| | PDF (177 KB) | HTML

For positive integers j ges k, an L(j, k)-labeling of a graph G is an integer labeling of its vertices such that adjacent vertices receive labels that differ by at least j and vertices that are distance two apart receive labels that differ by at least k. We determine lambdaj k(G) for the case when G is a Kronecker product of finitely many complete graphs, where there are cert... View full abstract»

• ### Block-Interlaced LDPC Decoders With Reduced Interconnect Complexity

Publication Year: 2008, Page(s):74 - 78
Cited by:  Papers (42)  |  Patents (1)
| | PDF (629 KB) | HTML

Two design techniques are proposed for high-throughput low-density parity-check (LDPC) decoders. A broadcasting technique mitigates routing congestion by reducing the total global wirelength. An interlacing technique increases the decoder throughput by processing two consecutive frames simultaneously. The brief discusses how these techniques can be used for both fully parallel and partially parall... View full abstract»

• ### Double-Binary Circular Turbo Decoding Based on Border Metric Encoding

Publication Year: 2008, Page(s):79 - 83
Cited by:  Papers (26)  |  Patents (5)
| | PDF (831 KB) | HTML

This brief presents an energy-efficient soft-input soft-output (SISO) decoder based on border metric encoding, which is especially suitable for nonbinary circular turbo codes. In the proposed method, the size of the branch memory is reduced to half and the dummy calculation is removed at the cost of a small-sized memory that holds encoded border metrics. Due to the infrequent accesses to the borde... View full abstract»

• ### A Compact Single-FPGA Fading-Channel Simulator

Publication Year: 2008, Page(s):84 - 88
Cited by:  Papers (16)
| | PDF (732 KB) | HTML

This brief presents a novel computationally efficient design and implementation of a Rayleigh flat fading-channel simulator. To generate complex Gaussian variates with the required U-shaped power spectrum, the simulator utilizes an infinite-impulse response (IIR) spectrum shaping filter followed by multistage interpolators and low-pass IIR filters. The new simulator significantly simplifies the ch... View full abstract»

• ### Synthesis of Cascaded Lossless Commensurate Lines

Publication Year: 2008, Page(s):89 - 91
Cited by:  Papers (3)
| | PDF (95 KB) | HTML

A scattering transfer matrix factorization based algorithm for cascaded lossless commensurate line synthesis is presented. The characteristic impedances of the extracted commensurate lines and the reflection factors of the remaining networks are formulated in terms of reflection factor coefficients of the whole circuit. There is no need to use root search routines so as to cancel common terms, to ... View full abstract»

• ### Power Waves and Conjugate Matching

Publication Year: 2008, Page(s):92 - 96
Cited by:  Papers (28)  |  Patents (1)
| | PDF (115 KB) | HTML

The concept of power waves gives more natural relations between incident and reflected power in a microwave network than the typically used traveling waves. The reflection coefficient for power waves directly describes the reflection of power whereas the reflection coefficient of traveling waves describes the reflection of the waves themselves. In this brief, new physical reasoning of power waves ... View full abstract»

• ### Order form for reprints

Publication Year: 2008, Page(s): 97
| PDF (337 KB)
• ### IEEE Transactions on Circuits and Systems—II: Express Briefs Information for authors

Publication Year: 2008, Page(s): 98
| PDF (33 KB)

Publication Year: 2008, Page(s):99 - 100
| PDF (1057 KB)

## Aims & Scope

Part I will now contain regular papers focusing on all matters related to fundamental theory, applications, analog and digital signal processing. Part II will report on the latest significant results across all of these topic areas.

Full Aims & Scope

## Meet Our Editors

Editor-in-Chief

Chi K. Michael Tse
Dept. of Electronic and Information Engineering
Hong Kong Polytechnic University
Hunghom, Hong Kong
cktse@ieee.org