IEEE Design & Test of Computers

Issue 1 • Feb. 1988

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Displaying Results 1 - 4 of 4
  • Chip-level modeling with HDLs

    Publication Year: 1988, Page(s):8 - 18
    Cited by:  Papers (12)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (766 KB)

    VLSI circuits have made gate-level modeling of large-scale systems impractical. Chip-level modeling offers an alternative approach to model development that still represents timing accurately. The authors examine this approach to modeling and the use of hardware description languages (HDLs) to achieve the desired accuracy. The characteristics of chip-level models are reviewed and sample models are... View full abstract»

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  • A workbench for computer architects

    Publication Year: 1988, Page(s):19 - 29
    Cited by:  Papers (17)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (933 KB)

    The authors present a high-level simulator that supports a top-down architectural analysis of embedded, custom applications. This tool characterizes more than 50 instruction-set variants and allows data such as instruction cached performance, data cache performance, register set size, and register allocation policy to be evaluated for all the architectures simultaneously. Designers also have more ... View full abstract»

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  • Using Ada as an HDL

    Publication Year: 1988, Page(s):30 - 42
    Cited by:  Papers (3)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (1062 KB)

    Ada can be used as both a hardware description language and a distributed simulation environment, which results in a uniform approach to the simulation of digital designs. Ada's synchronization constructs are used in conjunction with techniques for distributed modeling and scheduling to provide a distributed verifier. This technique has been verified for functional and fault simulation and for tim... View full abstract»

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  • A single-row transformation technique

    Publication Year: 1988, Page(s):43 - 47
    Cited by:  Papers (1)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (296 KB)

    A technique is presented for transforming channel and switch-box models to single-row routing (SSR) problems, which allows the use of powerful SSR techniques. This single-row transformation (SRT) technique produces a quality routing solution and reduces the number of vias required. The SRT technique can be used on these, and many other models, to reduce the time and effort required to accomplish t... View full abstract»

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This Periodical ceased production in 2012. The current retitled publication is IEEE Design & Test.

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Krishnendu Chakrabarty