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Circuits and Systems II: Analog and Digital Signal Processing, IEEE Transactions on

Issue 8 • Date Aug 1992

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Displaying Results 1 - 14 of 14
  • Error analysis in pipeline A/D converters and its applications

    Publication Year: 1992 , Page(s): 506 - 515
    Cited by:  Papers (5)  |  Patents (6)
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (752 KB)  

    The conversion error of a pipelined A/D converter using inaccurate comparators is analyzed. Error bounds are established, and it is shown that the error can be compensated using simple analog circuitry combined with some digital logic. The resulting system is especially useful for fast converters in which accurate compensators would require a large chip area and large DC power. Simulations are presented to verify the efficiency of the proposed error correction scheme View full abstract»

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  • Optimizing the stage resolution in pipelined, multistage, analog-to-digital converters for video-rate applications

    Publication Year: 1992 , Page(s): 516 - 523
    Cited by:  Papers (85)  |  Patents (14)
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (700 KB)  

    The author examines the effect of the stage resolution on some important characteristics of monolithic, pipelined, multistage, analog-to-digital converters (ADCs) with identical stages for video-rate applications. These characteristics are the linearity, speed, area, and power dissipation. It is found that although large stage resolution is desirable from a linearity standpoint, the effect of stage resolution on linearity is small if the ADC uses redundancy and digital correction and if the magnitude of the interstage gain is at least two. Also, minimizing the stage resolution maximizes the conversion rate and minimizes both the die area and the power dissipation View full abstract»

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  • A study of tuning for continuous-time filters using macromodels

    Publication Year: 1992 , Page(s): 524 - 531
    Cited by:  Papers (6)
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (748 KB)  

    Simulation of tuning of integrated continuous-time filters in a real circuit context, using macromodels, is described. The macromodels include circuit nonlinearities and bias-dependent parameters which are required for a study of tuning. The success in identifying and modeling the important parameters is demonstrated by the good agreement between macromodel and full transistor simulations. It is shown that a significant increase in simulation speed can be achieved View full abstract»

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  • Low roundoff noise augmented IIR filters based on normal realization

    Publication Year: 1992 , Page(s): 540 - 548
    Cited by:  Papers (2)  |  Patents (1)
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (632 KB)  

    As second-order normal subfilters can be expressed as first-order complex subfilters, the authors decompose IIR digital filters into a parallel combination of first-order complex subfilters, in which each subfilter is augmented with one complex pole-zero cancellation pair and realized in complex direct form II. Under the l2 dynamic range constraint, explicit expressions for the optimal complex pole-zero cancellation pair and the minimum roundoff noise of complex augmented subfilters are derived. Compared to normal realization, the noise reduction of this optimal complex augmented realization approaches its upper bound of about 6 dB as the desired filter bandwidth decreases. In addition, several suboptimal realizations are investigated and shown to achieve a greater performance-to-cost ratio View full abstract»

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  • Polyphase IIR decimation filter design for oversampled A/D converters with approximately linear phase

    Publication Year: 1992 , Page(s): 497 - 505
    Cited by:  Papers (1)  |  Patents (1)
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (644 KB)  

    The authors describe a polyphase IIR decimation filter design methodology for oversampled A/D converters by formulating a general nonlinear programming problem that optimizes magnitude response under certain phase linearity constraints. It provides the flexibility of maximizing the signal-to-noise (SNR) when quantization noise with an arbitrary spectral density is presented. A numerical method, the samples-sum-estimation (SSE) method, is introduced to simplify the objective function. Examples show that the proposed design enjoys at least a factor of two reduction in the multiplication rate when compared with conventional FIR filters. This implementation becomes more attractive for applications in modulators with multibit output such as the MASH modulator as well as Σ-Δ modulators with a multibit internal quantizer. The proposed design achieves a SNR of less than 1 dB from that obtained with an ideal low-pass filter at different decimation ratios while the group delay displays an approximately constant value View full abstract»

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  • CMOS device modeling for subthreshold circuits

    Publication Year: 1992 , Page(s): 532 - 539
    Cited by:  Papers (14)
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (604 KB)  

    Simple models of MOS device behavior that covers the subthreshold regime and the transition to above threshold are explored. A formulation that appears to provide results as good as process variation permits and that is well-suited to efficient computation is proposed. The exponential dependence of source-drain current on gate voltage in subthreshold implies that current values may be very sensitive to variation in parameter values (particularly those that appear in exponents). This problem is investigated, particularly with respect to threshold voltage, I0, and κ View full abstract»

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  • High speed CMOS POS PLA using predischarged OR array and charge sharing AND array

    Publication Year: 1992 , Page(s): 557 - 564
    Cited by:  Papers (12)  |  Patents (3)
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (672 KB)  

    A family of four PLAs using triggered decoders charge sharing is presented. They can be classified into two types. In the front of the OR-AND array, the two types 1 and 2 use 1-b or 2-b triggered decoders, respectively. Type 1 is a single-phase dynamic CMOS POS (NOT-NOT)-(NOT-NOR)-(NOT-NOT) PLAs in a product of sums (POS) using CMOS domino logic in the OR array and charge sharing logic in the AND array. Type 2 is a single-phase dynamic CMOS POS OR-(NOT-NOR)-(NOT-NOT) PLA in a POS using predischarged OR gates like NMOS domino logic and charge sharing logic. By using charge sharing for the implementation of a cascaded AND array in types 1 and 2, and by using a triggered input technique to replace ground switches, faster PLAs that require lower power dissipation than the conventional fastest CMOS SOP (NOT-NOR)-(NOT-NOT)-(NOR-NOT) PLA in a sum of products (SOP) are achieved. By using triggered 2-b decoders on the input during the precharge time, the capacitance of an input minterm of a PLA can be minimized to reduce power consumption View full abstract»

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  • Efficient systolic array implementations of IIR digital filtering

    Publication Year: 1992 , Page(s): 581 - 584
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (332 KB)  

    Techniques for overcoming the hardware inefficiency in the systolic array implementation of a generic class of IIR digital filters which include the classical direct form digital filter, the Gray-Markel digital lattice or ladder filters, and the Rao-Kailath orthogonal digital filters are discussed. The hardware inefficiency is due to the partial delay transfer and the time rescaling involved in pipelining those filter algorithms. The two schemes proposed improve the hardware efficiency to about 100% with low control overhead View full abstract»

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  • A 512 K-bit magneto resistive memory with switched capacitor self-referencing sensing

    Publication Year: 1992 , Page(s): 585 - 587
    Cited by:  Papers (5)  |  Patents (2)
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (260 KB)  

    A 512 K-bit nonvolatile magnetoresistive memory with a switched-capacitor self-referencing sensing scheme is reported. This memory is economical since it requires only one mask beyond a typical CMOS process and has rad hard, scalable, and no wear-out properties. This memory has a cell size of 2.0 μm×10 μm, logic buried under its cells, and a 0.3 cm2 die. It is useful for disk caches and for replacing plated wire memories in aerospace applications View full abstract»

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  • A CMOS square-law programmable floating resistor independent of the threshold voltage

    Publication Year: 1992 , Page(s): 565 - 574
    Cited by:  Papers (15)  |  Patents (1)
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (796 KB)  

    A CMOS architecture for a floating linear resistor which exploits the square-law model of the MOS transistor is presented. The architecture is programmable by DC control voltage and is easily modified such that it is threshold-voltage independent, allowing large signal handling and immunity to substrate noise. Design trade-offs and device size optimization are investigated. Second-order effects due to mobility degradation and channel length modulation are analyzed and a simple high frequency model for the resistor is developed. The architecture is fabricated in a 2 μm p-well CMOS MOSIS process. The resistor occupies 210 μm×270 μm, consumes 0.4-4.0 mW with ±5 V supply and exhibits a signal (at 1% THD) to noise ratio of more than 100 dB over a 1 V range of the DC control voltage View full abstract»

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  • Design of complex all-pass networks using Remez algorithm

    Publication Year: 1992 , Page(s): 549 - 556
    Cited by:  Papers (14)
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (488 KB)  

    A new method for designing complex all-pass digital filters is introduced. Phase error is regarded as the amplitude of complex error between the designed and the desired all-pass function. Then the Remez exchange algorithm is applied to the amplitude of complex error, and it is approximated to be equiripple. Although equiripple solutions to phase approximation problems are not necessarily optimum in the Chebyshev sense, considerable design experience shows that equiripple approximations are often quite satisfactory results. Such cases are considered, and it is shown that the best uniform phase approximation to an arbitrarily specified phase response can be found. In this algorithm, a satisfactory solution is obtained through a few iterations without any initial guess of the solution. Furthermore, as one of the complex all-pass digital filter applications, a large class of real coefficient doubly complementary IIR digital filter pairs is introduced by using a single complex all-pass digital filter, which has approximately linear phase View full abstract»

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  • An l1-approximation based method for synthesizing FIR filters

    Publication Year: 1992 , Page(s): 578 - 581
    Cited by:  Papers (2)
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (332 KB)  

    A method is proposed for the synthesis of digital filters having approximately the desired linear phase frequency responses. A mathematical optimization problem is formulated from the synthesis objective, and a theorem from the theory of l2-approximation is used to convert the optimization problem such that it can be solved by the linear programming technique. The method is successfully applied to the synthesis of a digital FIR equalizer for a given analog antialiasing filter View full abstract»

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  • Generalized sampling theorem

    Publication Year: 1992 , Page(s): 587 - 588
    Cited by:  Papers (19)  |  Patents (1)
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (148 KB)  

    It is shown, for an arbitrary function f(t), that if there exists a reversible function g(t) such that g(f(t)) is band-limited, then f(t) can be uniquely determined in terms of its samples f(nTs) sampled with the Nyquist rate of g(f(t)). The application of this result to undersampling is illustrated by examples View full abstract»

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  • Encoding don't cares in static and dynamic content-addressable memories

    Publication Year: 1992 , Page(s): 575 - 578
    Cited by:  Papers (10)  |  Patents (28)
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (280 KB)  

    An encoding scheme for don't cares using two binary static content-addressable memory (CAM) cells is presented. No extra hardware is required for the storage and retrieval of don't cares beyond the hardware necessary for binary write and match operations found in most commercial static CAMs. Besides the availability of proven hardware for binary CAM chips, this implementation has the advantage that both binary and ternary values can coexist in a single CAM word View full abstract»

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Aims & Scope

This title ceased production in 2003. The current updated title is IEEE Transactions on Circuits and Systems II: Express Briefs.

Full Aims & Scope