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Electron Devices, IEEE Transactions on

Issue 12 • Date Dec 1992

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Displaying Results 1 - 25 of 27
  • A full adder using resonant-tunneling hot electron transistors (RHETs)

    Page(s): 2707 - 2710
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (488 KB)  

    Full adders are demonstrated using InGaAs-In(AlGa)As RHETs. The RHET's emitter and base electrodes were self-aligned using a SiO2 sidewall and angled beam ion milling. The common-base current gain was about 0.9 and the emitter current peak-to-valley ratio was 10. The RHET full adder was constructed using a three-input exclusive-OR logic gate and a three-input majority logic gate. The authors confirmed normal operation of the full adder at 77 K. Only seven RHETs were needed for the full adder, about one-quarter of bipolar transistors that would have been required View full abstract»

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  • Breakdown-speed considerations in AlGaAs/GaAs heterojunction bipolar transistors with special collector designs

    Page(s): 2711 - 2719
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (768 KB)  

    The breakdown-speed tradeoffs of AlGaAs/GaAs HBTs with special collector designs are presented. Monte Carlo techniques and 1-D drift-diffusion modeling are used for speed and breakdown simulation, respectively. Base current reversal is indicative of breakdown and is used in conjunction with the (breakdown voltage/total transit time) figure of merit in order to set up HBT performance criteria. Conventional (n-) and inverted field (p-) collectors show a good speed-breakdown compromise over a limited collector current density. Equally good characteristics but over a broader current range can be obtained from collector launcher (δn +-n--δp+) HBTs. Undoped collector HBTs (i-δp+) operate best at low currents. Overall, the use of special collector structures does not always guarantee the best speed-breakdown performance View full abstract»

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  • A fully complementary BiCMOS technology for sub-half-micrometer microprocessor applications

    Page(s): 2733 - 2739
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (524 KB)  

    A modular process architecture has been adopted to develop a versatile yet manufacturable, single-poly, four-level metal, fully complementary BiCMOS technology for sub-0.5-μm microprocessor products. Both the poly-emitter vertical n-p-n and p-n-p bipolar transistors are integrated into a dual-poly (n+/p+) gate CMOS process flow. Using a collector pedestal implant in the emitter window, the n-p-n performance has been enhanced to 26 GHz. Lateral p-n-p and TiSi2 Schottky-barrier diode are also available for circuit applications. Stacking of the tungsten-plug contacts and vias are allowed in the multilevel metallization module. Comparing the CMOS and BiCMOS implementation of a 68030 critical path, 40% speed improvement at 3.3-V Vcc and a CMOS/BiCMOS crossover at 2.2 V have been obtained for this logic BiCMOS technology View full abstract»

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  • A comprehensive analytical model for metal-insulator-semiconductor (MIS) devices

    Page(s): 2771 - 2780
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (644 KB)  

    A comprehensive model for metal-insulator-semiconductor (MIS) devices under dark conditions which consists of a wide range of parameters has been developed. Parameters neglected by other authors have been included. The effects of surface states, silicon dioxide thickness, substrate doping, fixed oxide charges, substrate thickness, and metal work function are taken into account. The permittivity and barrier height of thin oxide are included in the calculation. The limits on equilibrium and nonequilibrium are explored View full abstract»

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  • Analytical modeling of oxide breakup effect on base current in n +-polysilicon emitter bipolar devices

    Page(s): 2797 - 2802
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (508 KB)  

    The authors have modeled the base current change with different percentages of broken interface-oxide area (interface void). A pseudo-two-dimensional structure of dual channels of minority-carrier transport at the interface between the polysilicon and the silicon emitter, is constructed in analogy with an electrically equivalent conductance network. Using the conductance network, an analytical expression of base current is easily derived. For typical polysilicon emitter devices of ~10-15 Å interface oxide, the experimental results show that the strong dependence of base current on the fraction of interface void can be modeled. The simulation predicts that the base current will be insensitive to the fraction of interface oxide breakup for very thin interface-oxide polysilicon emitter devices. Recent reports on finding a process window between current gain and emitter resistance optimization in a certain range of interface breakup ratios are confirmed by the model View full abstract»

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  • Submicrometer self-aligned AlGaAs/GaAs heterojunction bipolar transistor process suitable for digital applications

    Page(s): 2694 - 2700
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (716 KB)  

    A self-aligned process is developed to obtain submicrometer high-performance AlGaAs/GaAs heterojunction bipolar transistors (HBTs) which can maintain a high current gain for emitter sizes on the order of 1 μm2. The major features of the process are incorporation of an AlGaAs surface passivation structure around the entire emitter-base junction periphery to reduce surface recombination and reliable removal of base metal (Ti/W) deposits from the sidewall by electron cyclotron resonance (ECR) plasma deposition of oxide and ECR plasma etching by NF3. A DC current gain of more than 30 can be obtained for HBTs with an emitter-base junction area of 0.5×2 μm2 at submilliampere collector currents. The maximum fT and fmax obtained from a 0.5×2 μm2 emitter HBT are 46 and 42 GHz, respectively at IC=1.5 and more than 20 GHz even at IC=0.1 mA View full abstract»

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  • AlGaAs/GaAs double-heterostructure-emitter bipolar transistor (DHEBT)

    Page(s): 2740 - 2744
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (460 KB)  

    An AlGaAs/GaAs double-heterostructure-emitter bipolar transistor (DHEBT) fabricated by molecular beam epitaxy (MBE) is presented. The use of a structure symmetrical with respect to the base layer results in bidirectional transistor and switching behavior. Due to a significant area difference between emitter-base and base-collector junction, an asymmetrical property is observed. With an emitter edge-thinning design, the transistor performance may be further improved. A common-emitter current gain of up to 140 with a negligible collector-emitter offset voltage (~40 mV) is achieved. A bidirectional S-shaped negative-differential-resistance (NDA) phenomenon occurs at high V CE bias voltage. The temperature dependence of the NDR is investigated. A three-terminal-controlled switching device is found to perform well when the control current is introduced into the base electrode View full abstract»

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  • Inverted thin-film transistors with a simple self-aligned lightly doped drain structure

    Page(s): 2803 - 2809
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (700 KB)  

    The I-V characteristics of inverted thin-film transistors (TFT) are studied. A simple lightly doped drain (LDD) structure is utilized to control the channel electric field at the drain junction and to improve the performance of the TFTs. The LDD region is self-aligned to the channel and the source/drain regions. It is created by a spacer around an oxide mask which exclusively defines the channel length Lch. Experimental data show that the leakage current, subthreshold swing SS, saturation current, and on/off current ratio of the inverted TFTs are closed related to Lch, LLDD, the drain bias, gate voltage, and LDD dose. With a gate deposited at low temperature, a saturation current of ~1.25 μA at 5 V and a leakage current of ~0.03 pA per micrometer of channel width were achieved. The current ratio therefore exceeds seven orders of magnitude, with an SS of 380 mV/decade. At 3.3 V, the current ratio is ~7×106 View full abstract»

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  • On the reverse blocking characteristics of Schottky power diodes

    Page(s): 2813 - 2814
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (200 KB)  

    An analytical model for the reverse blocking characteristics of Schottky power diodes has been obtained by incorporating the impact ionization multiplication factor into the thermionic-emission reverse leakage current with field-dependent Schottky-barrier lowering. Excellent agreement has been found between calculated curves and measured data. This model allows the accurate calculation of the reverse-leakage current of Schottky diodes at high reverse voltage View full abstract»

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  • Analytical model of shot noise in double-barrier resonant-tunneling diodes

    Page(s): 2686 - 2693
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (684 KB)  

    The shot noise in double-barrier diodes is analyzed using the stationary-state approach to resonant tunneling through the first quasi-bound level. Significant deviations from full shot noise are predicted. Significant shot noise suppression occurs in the entire positive differential resistance region below the current peak, and shot noise enhancement occurs in the negative differential resistance region above the peak. The physical basis for these effects is assumed to be the modulation of the double-barrier transmission probability by charge stored in the first quasi-bound level in the quantum well. The analysis confirms microwave noise measurements of high-speed double-barrier diodes View full abstract»

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  • In0.52Al0.48As/In0.53Ga0.47 As MSM photodetectors and HEMT's grown by MOCVD on GaAs substrates

    Page(s): 2817 - 2818
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (184 KB)  

    The authors report the first demonstration of In0.52Al 0.48As/In0.53Ga0.47As metal-semiconductor-metal (MSM) photodetectors and high-electron-mobility transistors (HEMTs) grown on GaAs substrates by organometallic chemical vapor deposition. Both photodetectors and transistors showed no degradation in performance compared to devices simultaneously grown on InP substrates. The photodetectors exhibited a responsivity of 0.45 A/W and leakage current of 10 to 50 nA. The HEMTs with a gate length of 1.0 μm showed a transconductance as high as 250 mS/mm, and fT and fmax of 25 and 70 GHz, respectively View full abstract»

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  • Back-gate bias effect on the subthreshold behavior and the switching performance in an ultrathin SOI CMOS inverter operating at 77 and 300 K

    Page(s): 2781 - 2790
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    The effect of back-gate bias on the subthreshold behavior and the switching performance in an ultrathin SOI CMOS inverter operating at 300 and 77 K is investigated using a low-temperature device simulator. The simulation results show that the nonzero back-gate bias induces hole pile-up at the back interface, which causes opposite effects on the NMOS and PMOS subthreshold characteristics at 300 and 77 K. Throughout the transient process, at 300 K, for VB=-5 V operation, hole pile-up at the back interface always exists in the NMOS device. Compared to the zero back-gate bias case, at VB=-5 V, the risetime of the SOI CMOS inverter is over 5% shorter at 77 and 300 K and the falltime is 5% longer. Prepinch-off velocity saturation in the NMOS device dominates the pull-down transient as a result of the smaller electron critical electric field View full abstract»

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  • Characteristics of a new isolated p-well structure using thin epitaxy over the buried layer and trench isolation

    Page(s): 2758 - 2764
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    An isolated p-well structure for deep-submicrometer BiCMOS LSIs is proposed. The structure consists of a retrograde p-well in an n-type thin epitaxial layer over an n+ buried layer, and trench isolation. Latchup characteristics in this CMOS structure and breakdown characteristics of the shallow p-well are studied on test devices. Excellent latchup immunity and sufficient voltage tolerance are obtained with a thin 1-μm epitaxial layer. A CMOS 1/8 dynamic-type frequency divider using this well structure functions properly up to 3.2 GHz at a 2-V supply voltage View full abstract»

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  • A possible scaling limit for enhancement-mode GaAs MESFETs in DCFL circuits

    Page(s): 2681 - 2685
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (384 KB)  

    A possible scaling limit for ion-implanted GaAs MESFETs with buried p-layer LDD structure has been numerically investigated. A Schottky-contact model with a thin interfacial layer and interface states was used to simulate the Schottky-barrier height of a scaled-down MESFETs. When enhancement-mode MESFETs in direct-coupled FET logic (DCFL) circuits are scaled down, the gate length can be reduced to 0.21 μm at an interface-state density of 6.6×1012 cm-2·eV-1, when the barrier height is greater than 0.6 V, the threshold voltage is less than 0.1 V, and the channel aspect ratio is 8 View full abstract»

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  • Diode ideality factor for surface recombination current in AlGaAs/GaAs heterojunction bipolar transistors

    Page(s): 2726 - 2732
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (576 KB)  

    n-p-n AlGaAs/GaAs heterojunction bipolar transistors of various emitter areas have been fabricated to examine the diode ideality factor for surface recombination. These transistors are fabricated with and without exposed extrinsic base surfaces. Comparison of the measured results indicates that the base surface recombination current increases exponentially with the base-emitter voltage with an ideality factor which is closer to 1 than 2(1<n<1.33). This finding agrees with a published theoretical analysis of base surface recombination in HBTs. This study is compared with other experimental work View full abstract»

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  • Distributed modeling of switching transients in GaAs MESFET's

    Page(s): 2819 - 2821
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (296 KB)  

    The transient phenomena resulting from the application of a step bias at the gate electrode of a GaAs MESFET have been simulated using a two-dimensional model. Results emphasizing the effects of the displacement current in high-speed devices are presented. The causes of the delay are discussed for devices of different gate lengths, and the effects of the distributed gate capacitance and the related delay in the drain current characteristics are incorporated in an equivalent circuit model. Analytical expressions derived from large-signal analysis are shown to conform with the results of two-dimensional simulation, allowing for an implementation in simulators such as SPICE View full abstract»

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  • An analytical model for floating-gate MOSFET including the effects of the overlapping capacitance

    Page(s): 2821 - 2823
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    An analytical model for the current-voltage characteristics of a floating-gate MOSFET are developed. The effects of the overlapping capacitance are included. The model was tested on experimental data obtained from fabricated devices. Good agreement was observed between measurement results and the model View full abstract»

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  • Complete transient simulation of flash EEPROM devices

    Page(s): 2750 - 2757
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (684 KB)  

    A two-dimensional device simulator which allows the complete transient simulation of nonvolatile memories is presented. The simulator has been derived from HFIELDS and incorporates models to account for Fowler-Nordheim tunneling, hot electron injection through silicon dioxide, and band-to-band tunneling in silicon. The physical models have been verified by comparing simulations with measurements performed on suitable test structures where good agreement has been obtained. The tool has been used to investigate flash EEPROM device scaling and to evaluate a published scaling scenario View full abstract»

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  • 0.25-μm pseudomorphic HEMTs processed with damage-free dry-etch gate-recess technology

    Page(s): 2701 - 2706
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    Damage-free, dry-etched 0.25-μm T-shape gate pseudomorphic InGaAs channel HEMTs have been demonstrated. A Freon-12-based discharge was used in either electron cyclotron resonance (ECR) or reactive ion etching (RIE) systems to perform the gate recess process. Etching selectivity of more than 200 was obtained between the GaAs cap layer and the underlying AlGaAs donor layer. Self-bias voltages of -30 to -50 V were used in the etching process to minimize the damage. Pre- and post-etch clean steps were utilized to achieve uniform etch and removal of any dry-etch-related residues. Schottky diodes fabricated on n-GaAs subjected to either dry or wet etching showed no differences of barrier height, zero-bias depletion depth, and ideality factor. By using the dry etch for gate recess, very tight threshold voltage uniformity was obtained. The devices showed I-V characteristics comparable to that of devices fabricated with a wet chemical process View full abstract»

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  • Optimization of the tradeoff between switching speed of the internal diode and on-resistance in gold- and platinum-implanted power metal-oxide-semiconductor devices

    Page(s): 2745 - 2749
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (472 KB)  

    Diffusion of platinum and gold has been used to reduce minority-carrier lifetime in power metal-oxide-semiconductor devices in order to improve the switching characteristics of the internal diode. Gold thin-film deposition and gold- or platinum-ion implantation techniques have been adopted to realize the prediffusion source. For a given reduction in lifetime, the concomitant increase in the on-resistance of the device, as determined by the forward characteristics, is smaller in gold-implanted than in gold-deposited devices; an even smaller increase in on-resistance is obtained by using platinum implantation. Therefore, ion implantation of platinum in power MOS devices fabrication provides a better tradeoff between static characteristics of the devices and switching speed of their internal diodes View full abstract»

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  • A versatile stacked storage capacitor on FLOTOX cell for megabit NVRAM's

    Page(s): 2791 - 2796
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (444 KB)  

    A versatile stacked storage capacitor on FLOTOX (SCF) structure is proposed for a megabit nonvolatile DRAM (NV-DRAM) cell that has all the features required for NVRAMs. The SCF structure realizes a 30.94-μm 2 NV-DRAM cell with 0.8-μm design rules and allows an innovative flash store/recall (DRAM to EEPROM/EEPROM to DRAM) operation that does not disturb original data in DRAM or EEPROM. This store operation is completed in less than 10 ms. The single cell shows excellent reliability such as store endurance greater than 106 cycles and EEPROM data retention in excess of 10 years under high storage temperatures of 150°C and DRAM write operation at 85°C. The SCF cell has been successfully implemented into the 1 Mb NVRAM View full abstract»

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  • The vertical integration of crystalline NMOS and amorphous orientational edge detector

    Page(s): 2810 - 2812
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    The integration of the amorphous silicon (a-Si:H) orientational edge detector on top of the crystalline silicon metal-oxide-semiconductor (MOS) transistor has been achieved. The edge detector is an effective input device for pattern recognition in which only the skeleton of the object will be extracted, while the underlying MOSFET can amplify the response of the edge detector and perform further analysis. This integration can be viewed as a key step in combining crystalline silicon readout circuit and amorphous silicon edge detector to form three-dimensional architecture. It is a promising technique for future application in neural image sensors View full abstract»

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  • Entirely gate-surrounded MOS capacitor to study the intrinsic oxide quality

    Page(s): 2814 - 2816
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (256 KB)  

    The intrinsic dielectric strength of gate oxides is investigated by MOS capacitors which are designed so that the gate poly does not cross the field oxide edge. Using the charge to breakdown in the high-injection regime as a sensitive indicator, it is shown that poly-surrounded capacitors are required to measure the intrinsic oxide quality, whereas conventional devices may be sensitive to process variations in the MOS isolation sequence and oxide thinning at the field oxide edge View full abstract»

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  • The Einstein relation for degenerate semiconductors with nonuniform band structures

    Page(s): 2826 - 2828
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (216 KB)  

    Modification of the Einstein equation for semiconductors with nonparabolic energy bands and doped nonuniformly with impurity atoms is suggested. The suggestion is based on a new approximation of the Fermi-Dirac integral of order 1/2, namely, F1/2n), where ηn is the reduced Fermi level for electrons. The relation reduces to that for semiconductors with parabolic energy bands and doped uniformly with impurity atoms under appropriate boundary conditions. A comparison of the calculated and exact results for F1/2(η) is found to be very encouraging View full abstract»

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  • Bias-dependent collapse and its recovery phenomenon in AlGaAs/GaAs 2DEGFETs at low temperatures

    Page(s): 2720 - 2725
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (540 KB)  

    Current-voltage characteristics for AlGaAs/GaAs 2DEGFETs (two-dimensional electron gas FETs) have been investigated at low temperatures in terms of stress biases and stress time. The study reveals that the degree of collapse strongly depends on the magnitude of the stress drain voltage. The device exhibits seriously collapsed I -V characteristics when the stress drain voltage is chosen at around 1.2 V. Application of higher stress drain voltages leads to less distorted I-V characteristics, demonstrating a collapse-recovery mechanism without the need for illuminating or heating the device, and therefore the heavily collapsed state and the recovered state can be switched with each other by simply changing the value of the stress drain voltage. Based on the gate current analysis during the bias stress step, the authors attribute the mechanism responsible for the drain-stress-induced recovery phenomenon to the ionization of DX centers by capture of holes generated by impact ionization View full abstract»

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IEEE Transactions on Electron Devices publishes original and significant contributions relating to the theory, modeling, design, performance and reliability of electron and ion integrated circuit devices and interconnects.

 

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Acting Editor-in-Chief

Dr. Paul K.-L. Yu

Dept. ECE
University of California San Diego