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Electron Devices, IEEE Transactions on

Issue 12 • Date Dec. 2007

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Displaying Results 1 - 25 of 52
  • Table of contents

    Publication Year: 2007 , Page(s): C1 - 3114
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  • IEEE Transactions on Electron Devices publication information

    Publication Year: 2007 , Page(s): C2
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  • Changes to the Editorial Board

    Publication Year: 2007 , Page(s): 3115
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  • Kudos to Our Reviewers

    Publication Year: 2007 , Page(s): 3116
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  • 2007 Golden List of Reviewers

    Publication Year: 2007 , Page(s): 3117 - 3136
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (107 KB)  

    Lists the reviewers who contributed to IEEE Transactions on Electron Devices in 2007. View full abstract»

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  • Confidentiality of the Review Process

    Publication Year: 2007 , Page(s): 3137
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  • Design and Fabrication of 4H-SiC RF MOSFETs

    Publication Year: 2007 , Page(s): 3138 - 3145
    Cited by:  Papers (2)
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (546 KB) |  | HTML iconHTML  

    We present simulations, fabrication and analysis of 4H-SiC RF power MOSFETs. We obtain an extrinsic transition frequency of 11.2 GHz and an /max = 11.9 GHz, a breakdown voltage above 200 V and an output power of 1.9 W/mm at 3 GHz. The measured devices are double fingered, source-gate-drain-gate-source with 2times0.4 mm total gate width and the nominal channel length of the devices is 0.5 mum. To the authors knowledge, this is the highest transition frequency and output power density ever reported for SiC RF MOSFETs. The antipunch through is introduced as a way to take advantage of the SiC's material properties. A detailed description of the device processing is also given. View full abstract»

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  • Voltage-Polarity-Independent and High-Speed Resistive Switching Properties of V-Doped SrZrO3 Thin Films

    Publication Year: 2007 , Page(s): 3146 - 3151
    Cited by:  Papers (24)
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (251 KB) |  | HTML iconHTML  

    In this paper, nonpolar resistive switching behavior is reported for the first time in a SZO-based memory device. The electrode materials used which have different conductivities affect the resistive switching properties of the device. The Al/V:SZO-LNO/Pt device shows nonpolar switching behavior, whereas the Al/V:SZO/LNO device has bipolar switching property. The resistance ratios of these two devices are quite distinct owing to the difference between the resistance of low resistance states. The Al/V:SZO-LNO/Pt device with lower resistive switching voltages (mnplus7 V turn on and mnplus2 V turn off) and higher resistance ratio is more suitable for practical applications compared to the Al/V:SZO/LNO device. The switching speed of the Al/V:SZO-LNO/Pt device is 10 ns, which is the fastest speed that has ever been reported. The conduction mechanisms, nondestructive readout property, retention time, and endurance of this device are also reported in this paper. View full abstract»

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  • Thermal Boundary Resistance Between GaN and Substrate in AlGaN/GaN Electronic Devices

    Publication Year: 2007 , Page(s): 3152 - 3158
    Cited by:  Papers (33)
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (270 KB) |  | HTML iconHTML  

    The influence of a thermal boundary resistance (TBR) on temperature distribution in ungated AlGaN/GaN field-effect devices was investigated using 3-D micro-Raman thermography. The temperature distribution in operating AlGaN/GaN devices on SiC, sapphire, and Si substrates was used to determine values for the TBR by comparing experimental results to finite-difference thermal simulations. While the measured TBR of about 3.3 x 10-8 W-1 ldr m2 ldr K for devices on SiC and Si substrates has a sizeable effect on the self-heating in devices, the TBR of up to 1.2 x 10-8 W-1 ldr m2 ldr K plays an insignificant role in devices on sapphire substrates due to the low thermal conductivity of the substrate. The determined effective TBR was found to increase with temperature at the GaN/SiC interface from 3.3 x 10-8 W-1 ldr m2 ldr K at 150degC to 6.5 x 3.3 x 10-8 W-1 ldr m2 ldr K at 275degC, respectively. The contribution of a low-thermal-conductivity GaN layer at the GaN/substrate interface toward the effective TBR in devices and its temperature dependence are also discussed. View full abstract»

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  • Atomistic Modeling of Gate-All-Around Si-Nanowire Field-Effect Transistors

    Publication Year: 2007 , Page(s): 3159 - 3167
    Cited by:  Papers (8)
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (393 KB) |  | HTML iconHTML  

    We report atomistic simulations of the transport properties of Si-nanowire (SiNW) field-effect transistors. Results have been obtained within a self-consistent approach based on the nonequilibrium Green's function (NEGF) scheme in the density functional theory framework. We analyze in detail the operation of an ultrascaled SiNW channel device and study the characteristics and transfer characteristics behavior of the device while varying several parameters including doping, gate and oxide lengths, and temperature. We focus our attention to the quantum capacitance of the SiNW and show that a well-tempered device design can be accomplished in this regime by choosing suitable doping profiles and gate contact parameters. View full abstract»

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  • Full-Band Tunneling in High-κ Oxide MOS Structures

    Publication Year: 2007 , Page(s): 3168 - 3176
    Cited by:  Papers (8)
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (361 KB) |  | HTML iconHTML  

    In this paper, we investigate the tunneling properties of ZrO2 and HfO2 high-k oxides, by applying quantum mechanical methods that include the full-band structure of Si and oxide materials. Semiempirical sp3s*d tight-binding parameters have been determined to reproduce ab-initio band dispersions. Transmission coefficients and tunneling currents have been calculated for Si/ZrO2/Si and Si/HfO2/Si MOS structures, showing a very low gate leakage current in comparison to SiO2-based structures with the same equivalent oxide thickness. The complex band structures of ZrO2 and HfO2 have been calculated and used to develop an energy-dependent effective tunneling mass model. We show that effective mass calculations based on this model yield tunneling currents in close agreement with full-band results. View full abstract»

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  • Partial Crystallization of HfO2 for Two-Bit/Four-Level SONOS-Type Flash Memory

    Publication Year: 2007 , Page(s): 3177 - 3185
    Cited by:  Papers (6)
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (786 KB) |  | HTML iconHTML  

    The nonvolatile memory properties of the partially crystallized HfO2 charge storage layer are investigated using short-channel devices of gate length Lg down to 80 nm. Highly efficient two-bit and four-level device operation is demonstrated by channel hot electron injection programming and hot hole injection erasing for devices of Lg > 170 nm, although the reduction of the memory window is observed for devices of Lg < 170 nm. A memory window of 5.5 V, ten-year retention of Vth clearance larger than 1.5 V between adjacent levels, endurance for 105 programming/erasing cycles, and immunity to programming disturbances are demonstrated. Flash memory with partially crystallized HfO2 shows a larger memory window than HfO2 nanodot memory, assisted by the enhanced electron capture efficiency of an amorphous HfO2 matrix, which is lacking in other types of reported nanodot memory. The scalability, programming speed, Vth control for two-bit and four-level operation, endurance, and retention are also improved, compared with NROM devices that use a Si3N4 trapping layer. View full abstract»

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  • A Compact SPICE Model for Carbon-Nanotube Field-Effect Transistors Including Nonidealities and Its Application—Part I: Model of the Intrinsic Channel Region

    Publication Year: 2007 , Page(s): 3186 - 3194
    Cited by:  Papers (132)
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (813 KB) |  | HTML iconHTML  

    This paper presents a circuit-compatible compact model for the intrinsic channel region of the MOSFET-like single-walled carbon-nanotube field-effect transistors (CNFETs). This model is valid for CNFET with a wide range of chiralities and diameters and for CNFET with either metallic or semiconducting carbon-nanotube (CNT) conducting channel. The modeled nonidealities include the quantum confinement effects on both circumferential and axial directions, the acoustical/optical phonon scattering in the channel region, and the screening effect by the parallel CNTs for CNFET with multiple CNTs. In order to be compatible with both large-(digital) and small-signal (analog) applications, a complete transcapacitance network is implemented to deliver the real-time dynamic response. This model is implemented with an HSPICE. Using this model, we project a 13 times CV/I improvement of the intrinsic CNFET with (19, 0) CNT over the bulk n-type MOSFET at the 32-nm node. The model described in this paper serves as a starting point toward the complete CNFET-device model incorporating the additional device/circuit-level non-idealities and multiple CNTs reported in the paper of Deng and Wong. View full abstract»

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  • A Compact SPICE Model for Carbon-Nanotube Field-Effect Transistors Including Nonidealities and Its Application—Part II: Full Device Model and Circuit Performance Benchmarking

    Publication Year: 2007 , Page(s): 3195 - 3205
    Cited by:  Papers (113)
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (886 KB) |  | HTML iconHTML  

    This paper presents a complete circuit-compatible compact model for single-walled carbon-nanotube field-effect transistors (CNFETs) as an extension to Part 1 of this two-part paper. For the first time, a universal circuit-compatible CNFET model including the practical device nonidealities is implemented with HSPICE. In addition to the nonidealities included in the companion paper, this paper includes the elastic scattering in the channel region, the resistive source/drain (S/D), the Schottky-barrier resistance, and the parasitic gate capacitances. More than one nanotube per device can be modeled. Compared to silicon technology, the CNFETs show much better device performance based on the intrinsic gate-delay metric (six times for nFET and 14 times for pFET) than the MOSFET device at the 32-nm node, even with device nonidealities. This large speed improvement is significantly degraded (by a factor of five to eight) by interconnect capacitance in a real circuit environment. We performed circuit-performance comparison with all the standard digital library cells between CMOS random logic and CNFET random logic with HSPICE simulation. Compared to CMOS circuits, the CNFET circuits with one to ten carbon nanotubes per device is about two to ten times faster, the energy consumption per cycle is about seven to two times lower, and the energy-delay product is about 15-20 times lower, considering the realistic layout pattern and the interconnect wiring capacitance. View full abstract»

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  • Performance Comparisons Between Carbon Nanotubes, Optical, and Cu for Future High-Performance On-Chip Interconnect Applications

    Publication Year: 2007 , Page(s): 3206 - 3215
    Cited by:  Papers (31)
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (972 KB) |  | HTML iconHTML  

    Optical interconnects and carbon nanotubes (CNTs) present promising options for replacing the existing Cu-based global/semiglobal (optics and CNT) and local (CNT) wires. We quantify the performance of these novel interconnects and compare it with Cu/low-kappa wires for future high-performance integrated circuits. We find that for a local wire, a CNT bundle exhibits a smaller latency than Cu for a given geometry. In addition, by leveraging the superior electromigration properties of CNT and optimizing its geometry, the latency advantage can be further amplified. For semiglobal and global wires, we compare both optical and CNT options with Cu in terms of latency, energy efficiency/power dissipation, and bandwidth density. The above trends are studied with technology node. In addition, for a future technology node, we compare the relationship between bandwidth density, power density, and latency, thus alluding to the latency and power penalty to achieve a given bandwidth density. Optical wires have the lowest latency and the highest possible bandwidth density using wavelength division multiplexing, whereas a CNT bundle has a lower latency than Cu. The power density comparison is highly switching activity (SA) dependent, with high SA favoring optics. At low SA, optics is only power efficient compared to CNT for a bandwidth density beyond a critical value. Finally, we also quantify the impact of improvement in optical and CNT technology on the above comparisons. A small monolithically integrated detector and modulator capacitance for optical interconnects (~10 fF) yields a superior power density and latency even at relatively lower SA (~20%) but at high bandwidth density. At lower bandwidth density and SA lower than 20%, an improvement in mean free path and packing density of CNT can render it most energy efficient. View full abstract»

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  • Design and Fabrication of Monolithic Distributed Traveling-Wave Photodetectors Integrated With Polymer Optical Waveguides

    Publication Year: 2007 , Page(s): 3216 - 3222
    Cited by:  Papers (2)
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (435 KB) |  | HTML iconHTML  

    We have designed and fabricated monolithic distributed balanced traveling-wave metal-semiconductor-metal photodetectors (MSM PDs) distributed along single-mode polymer optical waveguides. We demonstrate that monolithically integrated polymer optical waveguides on a semiconductor can provide efficient optical interconnects in an optoelectronic circuit. A responsivity of 0.44 A/W and a 3-dB bandwidth of 10 GHz were obtained in a PD array with five MSM PDs. A high photocurrent of 7.3 mA was measured in an array having eight MSM PDs. Impulse response measurements were performed and the results were compared with frequency domain results. View full abstract»

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  • Capacitance–Voltage and Current–Voltage Measurements of Nitride Light-Emitting Diodes

    Publication Year: 2007 , Page(s): 3223 - 3228
    Cited by:  Papers (3)
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (196 KB) |  | HTML iconHTML  

    Capacitance-voltage (C-V ) and current-voltage (I-V) characteristics of nitride light-emitting diodes were measured. The apparent carrier distributions obtained from the C-V curves yielded much information about the samples, including information about the presence of acceptor-like defects in the active layer and the problem of electron overflow. The inconsistency between the experimental and simulated I-V curves also supported the presence of the defects. After compensating the acceptor-like defects by Si dopants and adjusting the overlap between the depletion region and the light-emitting structure, device performance was improved. View full abstract»

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  • CMOS-Based Active Pixel for Low-Light-Level Detection: Analysis and Measurements

    Publication Year: 2007 , Page(s): 3229 - 3237
    Cited by:  Papers (12)  |  Patents (60)
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (906 KB) |  | HTML iconHTML  

    An analysis of the active pixel sensor (APS), considering the doping profiles of the photodiode in an APS fabricated in a 0.18 mum standard CMOS technology, is presented. A simple and accurate model for the junction capacitance of the photodiode is proposed. An analytic expression for the output voltage of the APS obtained with this capacitance model is in good agreement with measurements and is more accurate than the models used previously. A different mode of operation for the APS based on the dc level of the output is suggested. This new mode has better low-light-level sensitivity than the conventional APS operating mode, and it has a slower temporal response to the change of the incident light power. At 1 muW/cm2 and lower levels of light, the measured signal-to-noise ratio (SNR) of this new mode is more than 10 dB higher than the SNR of previously reported APS circuits. Also, with an output SNR of about 10 dB, the proposed dc level is capable of detecting light powers as low as 20 nW/cm2, which is about 30 times lower than the light power detected in recent reports by other groups. View full abstract»

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  • A Novel Blocking Technology for Improving the Short-Channel Effects in Polycrystalline Silicon TFT Devices

    Publication Year: 2007 , Page(s): 3238 - 3244
    Cited by:  Papers (8)
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (1258 KB) |  | HTML iconHTML  

    An original blocking technology is proposed for improving the short-channel characteristics of polycrystalline silicon thin-film transistors (poly-Si TFTs). In particular, two types of modified devices called poly-Si TFT with block oxide and poly-Si on partial insulator (POPI)-TFT are designed for the first time in this field to enhance device performance. The proposed TFT structures can significantly reduce short-channel effects when compared with a thick source/drain (S/D) poly-Si TFT (i.e., the fully depleted TFT). In addition, an ultrathin (UT) S/D structure (UT-TFT) is designed to verify that the block oxide TFT devices do achieve improved performance without needing the thin active layers and ultrashallow junction depth. Also, the POPI-TFT is found to reduce the thermal instability through its natural body-tied scheme. View full abstract»

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  • Reversible Degradation of Ohmic Contacts on p-GaN for Application in High-Brightness LEDs

    Publication Year: 2007 , Page(s): 3245 - 3251
    Cited by:  Papers (10)
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (264 KB) |  | HTML iconHTML  

    This paper analyzes the high-temperature long-term stability of ohmic contacts on p-type gallium nitride (p-GaN). The contributions of the ohmic contacts and semiconductor material degradation are separated by adopting the transmission line method (TLM). Before stress, the current-voltage (I-V) curves measured at the pads of the TLMs showed a linear shape, indicating a good ohmic behavior of the contacts. Thermal treatment at 250degC was found to induce the worsening of the electrical characteristics of the contacts: identified degradation modes consist of a shift of the I-V curves toward higher voltages and strong nonlinearity of the characteristics around zero. This paper shows that the high-temperature instabilities of ohmic contacts on p-GaN are related to the interaction between the device surface and the plasma-enhanced chemical vapor deposition SiN passivation layer. Hydrogen contained in the passivation layer is supposed to play an important role in the degradation process: the interaction with the acceptor dopant at the metal/semiconductor interface induces the decrease of the effective acceptor concentration. As a consequence, both the ohmic contact characteristics and the semiconductor sheet resistance are worsened. View full abstract»

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  • Silicon Germanium CMOS Optoelectronic Switching Device: Bringing Light to Latch

    Publication Year: 2007 , Page(s): 3252 - 3259
    Cited by:  Papers (8)  |  Patents (15)
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (726 KB) |  | HTML iconHTML  

    We propose a novel semiconductor optoelectronic (OE) switch that is a fusion of a Ge optical detector and a Si metal-oxide-semiconductor (MOS) field-effect transistor (FET). The device operation principle is investigated, and the performance is explored by simulations. The proof of principle is demonstrated by experiments. The use of Ge enables operation in standard telecommunication wavelengths, in addition to providing the surrounding Si circuitry with noise immunity from signaling. The transconductance of the FET provides amplification, and an experimental current gain of up to 1000 is demonstrated. A complementary function is shown by tailoring the doping profiles. The circuit performance of a complementary pair using the International Technology Roadmap for Semiconductors values for the 150-nm node is evaluated by simulation, yielding ~100-ps cycle times. The switch can be fabricated in the nanoscale regime along with a high-performance Si complementary MOS. A very low capacitance can be achieved due to the isolation of the detection region from the current drive. OE conversion that is performed with such a compact device offers the potential of inserting light at the latch level in a microprocessor. View full abstract»

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  • Influence of Terrestrial Cosmic Rays on the Reliability of CCD Image Sensors—Part 1: Experiments at Room Temperature

    Publication Year: 2007 , Page(s): 3260 - 3266
    Cited by:  Papers (9)
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (674 KB) |  | HTML iconHTML  

    An aging effect in solid-state image sensors is studied: the generation of hard errors resulting in hot spots, warm pixels, or white pixels. These effects even occur in image sensors that are simply stored on the shelf. This paper describes experiments that are set up to prove that the main origin can be found with neutrons that create displacement damage in the silicon bulk. These neutrons are part of terrestrial cosmic rays. This statement is based on measurements done on devices that we stored on the shelf, that were flown around the world in airplanes, that were stored at high altitude, and that were stored in an underground laboratory. The creation of the hot spots is independent of technology, architecture, sensor type, or sensor vendor, and it is observed in charge-coupled devices as well as in complementary metal-oxide-semiconductor image sensors. In other words, it is a typical issue of the semiconductor base material: silicon! The paper is split up into two parts: this paper (part 1) describes the experiments done at room temperature, part 2 will concentrate on experiments done at higher temperatures. View full abstract»

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  • Defect Passivation With Fluorine and Interface Engineering for Hf-Based High- k/Metal Gate Stack Device Reliability and Performance Enhancement

    Publication Year: 2007 , Page(s): 3267 - 3275
    Cited by:  Papers (14)
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (1323 KB) |  | HTML iconHTML  

    Using a fluorinated high-fc/metal gate stack combined with a stress relieved preoxide (SRPO) pretreatment before high-fc deposition, we show significant device reliability and performance improvements. This is a critical result since threshold voltage instability may be a fundamental problem, and performance degradation for high-fc is a concern. The novel fluorinated TaxCy/HfZrOx/SRPO gate stack device exceeds the positive-bias-temperature-instability and negative-bias-temperature-instability targets with sufficient margin and has electron mobility at 1 MV/cm comparable to the industrial high-quality polySi/SiON device on bulk silicon. View full abstract»

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  • Stress Power Dependent Self-Heating Degradation of Metal-Induced Laterally Crystallized n-Type Polycrystalline Silicon Thin-Film Transistors

    Publication Year: 2007 , Page(s): 3276 - 3284
    Cited by:  Papers (14)
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (1196 KB) |  | HTML iconHTML  

    Self-heating degradation of n-type metal-induced laterally crystallized polycrystalline silicon thin-film transistors is systematically investigated under various stress powers. A two-stage degradation behavior with turnaround effect at the initial stage is characterized. The initial degradation stage is related to breaking of weak Si–H bonds. The floating-body effect by released hydrogen ions is responsible for the observed backshift of the transfer curve during the initial stress. On the other hand, the normal degradation stage occurs by breaking of strong Si–Si bonds and trap generation at grain boundaries (GBs) and the gate oxide/channel interface. Our model is supported by observed different activation energies related to two degradation stages and a direct observation of the continuous increase in GB trap density during the normal degradation. Furthermore, during the normal degradation stage, an anomalous continuous field-effect mobility increase along with its V_{g} dependence shift is first observed. It is clarified that this behavior is not a true channel mobility increase, but a consequence of stress-related trap generation. View full abstract»

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  • A Detailed Qualitative Model for the Programming Physics of Silicided Polysilicon Fuses

    Publication Year: 2007 , Page(s): 3285 - 3291
    Cited by:  Papers (2)  |  Patents (11)
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (844 KB) |  | HTML iconHTML  

    This paper presents a detailed qualitative model for the programming physics of 90-nm silicided polysilicon fuses that is derived from a wide range of measurement data. These insights have led to a programming time of 100 ns, while achieving a resistance increase of times. This is an order of magnitude better than any previously published result for the programming time and resistance increase individually. Simple calculations and TEM-analyses substantiate the proposed programming mechanism. The insights explain the importance of the falling edge of the programming pulse. The advantage of a rectangular fuse head over a tapered fuse head is shown and explained. Polysilicon doping type is shown to have little influence on the programming result. Finally, the stability of fuses programmed with this method is shown to be very high. This paper is an extended version of a work published previously and provides a more detailed description of the programming physics, additional insight into the influence of the edges of the programming pulse, the effect of doping and the stability of the devices after programming. View full abstract»

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Aims & Scope

IEEE Transactions on Electron Devices publishes original and significant contributions relating to the theory, modeling, design, performance and reliability of electron and ion integrated circuit devices and interconnects.

 

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Meet Our Editors

Acting Editor-in-Chief

Dr. Paul K.-L. Yu

Dept. ECE
University of California San Diego