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IEEE Transactions on Very Large Scale Integration (VLSI) Systems

Issue 12 • Date Dec. 2007

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Displaying Results 1 - 13 of 13
  • Table of contents

    Publication Year: 2007, Page(s): C1
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  • IEEE Transactions on Very Large Scale Integration (VLSI) Systems publication information

    Publication Year: 2007, Page(s): C2
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  • Efficient Modeling of Transmission Lines With Electromagnetic Wave Coupling by Using the Finite Difference Quadrature Method

    Publication Year: 2007, Page(s):1289 - 1302
    Cited by:  Papers (1)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (1277 KB) | HTML iconHTML

    This paper proposes an efficient numerical technique, called the finite difference quadrature (FDQ) method, to model the transmission line with radiated electromagnetic (EM) wave noise coupling. A discrete modeling approach, the FDQ method adapts coarse grid points along the transmission line to compute the finite difference between adjacent grid points. A global approximation scheme is formulated... View full abstract»

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  • Optimization of Pattern Matching Circuits for Regular Expression on FPGA

    Publication Year: 2007, Page(s):1303 - 1310
    Cited by:  Papers (31)  |  Patents (16)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (583 KB) | HTML iconHTML

    Regular expressions are widely used in the network intrusion detection system (NIDS) to represent attack patterns. Previously, many hardware architectures have been proposed to accelerate regular expression matching using field-programmable gate array (FPGA) because FPGAs allow updating of new attack patterns. Because of the increasing number of attacks, we need to accommodate a large number of re... View full abstract»

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  • PMOS-Only Sleep Switch Dual-Threshold Voltage Domino Logic in Sub-65-nm CMOS Technologies

    Publication Year: 2007, Page(s):1311 - 1319
    Cited by:  Papers (11)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (684 KB) | HTML iconHTML

    A circuit technique is proposed in this paper for simultaneously reducing the subthreshold and gate oxide leakage power consumption in domino logic circuits. Only p-channel sleep transistors and a dual-threshold voltage CMOS technology are utilized to place an idle domino logic circuit into a low leakage state. Sleep transistors are added to the dynamic nodes in order to reduce the subthreshold le... View full abstract»

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  • Analytical Techniques for Soft Error Rate Modeling and Mitigation of FPGA-Based Designs

    Publication Year: 2007, Page(s):1320 - 1331
    Cited by:  Papers (28)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (1169 KB) | HTML iconHTML

    Radiation-induced soft errors are the major reliability threat for digital VLSI systems. In particular, field-programmable gate-array (FPGA)-based designs are more susceptible to soft errors compared to application-specific integrated circuit implementations, since soft errors in configuration bits of FPGAs result in permanent errors in the mapped design. In this paper, we present an analytical ap... View full abstract»

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  • Wire Sizing and Spacing for Lithographic Printability and Timing Optimization

    Publication Year: 2007, Page(s):1332 - 1340
    Cited by:  Papers (3)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (795 KB) | HTML iconHTML

    As the VLSI feature size has already decreased below lithographic wavelength, the printability problem, due to strong diffraction effects, poses a serious threat to the progress of VLSI technology. A circuit layout with poor printability implies that it is difficult to make the printed features on wafers follow designed shapes without distortions. The development of resolution enhancement techniqu... View full abstract»

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  • A Design-for-Digital-Testability Circuit Structure for Σ- ∆ Modulators

    Publication Year: 2007, Page(s):1341 - 1350
    Cited by:  Papers (14)  |  Patents (2)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (1135 KB) | HTML iconHTML

    A design-for-digital-testability (DfDT) switched-capacitor circuit structure for testing Sigma-Delta modulators with digital stimuli is presented to reduce the overall testing cost. In the test mode, the DfDT circuits are reconfigured as a one-bit digital-to-charge converter to accept a repetitively applied Sigma-Delta modulated bit-stream as its stimulus. The single-bit characteristic ensures tha... View full abstract»

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  • Temporal Partitioning Data Flow Graphs for Dynamically Reconfigurable Computing

    Publication Year: 2007, Page(s):1351 - 1361
    Cited by:  Papers (11)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (822 KB) | HTML iconHTML

    FPGA-based configurable computing machines are evolving rapidly in large signal processing applications due to flexibility and high performance. In this paper, given a reconfigurable processing unit (RPU) with a logic capacity of ARPU and a computational task represented by a data flow graph G = (V, E, W), we propose a network flow-based multiway task partitioning algorithm to minimize ... View full abstract»

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  • Speedups and Energy Reductions From Mapping DSP Applications on an Embedded Reconfigurable System

    Publication Year: 2007, Page(s):1362 - 1366
    Cited by:  Papers (3)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (435 KB) | HTML iconHTML

    This paper presents performance improvements and energy savings from mapping real-world benchmarks on an embedded single-chip platform that includes coarse-grained reconfigurable logic with a microprocessor. The reconfigurable hardware is a 2-D array of processing elements connected with a mesh-like network. Analytical results derived from mapping seven real-life digital signal processing applicat... View full abstract»

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  • 2007 Index IEEE Transactions on Very Large Scale Integration (VLSI) Systems Vol. 15

    Publication Year: 2007, Page(s):1367 - 1384
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  • IEEE Transactions on Very Large Scale Integration (VLSI) Systems society information

    Publication Year: 2007, Page(s): C3
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  • IEEE Transactions on Very Large Scale Integration (VLSI) Systems Information for authors

    Publication Year: 2007, Page(s): C4
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Aims & Scope

Design and realization of microelectronic systems using VLSI/ULSI technologies requires close collaboration among scientists and engineers in the fields of systems architecture, logic and circuit design, chips and wafer fabrication, packaging, testing, and systems applications. Generation of specifications, design, and verification must be performed at all abstraction levels, including the system, register-transfer, logic, circuit, transistor, and process levels. To address this critical area through a common forum, the IEEE Transactions on VLSI Systems was founded.

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Meet Our Editors

Editor-in-Chief

Krishnendu Chakrabarty
Department of Electrical Engineering
Duke University
Durham, NC 27708 USA
Krish@duke.edu