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Computer-Aided Design of Integrated Circuits and Systems, IEEE Transactions on

Issue 12 • Date Dec. 2007

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Displaying Results 1 - 16 of 16
  • Table of contents

    Publication Year: 2007 , Page(s): C1 - C4
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  • IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems publication information

    Publication Year: 2007 , Page(s): C2
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  • Hierarchical Harmonic-Balance Methods for Frequency-Domain Analog-Circuit Analysis

    Publication Year: 2007 , Page(s): 2089 - 2101
    Cited by:  Papers (6)
    Save to Project icon | Request Permissions | Click to expandAbstract | PDF file iconPDF (997 KB) |  | HTML iconHTML  

    As a widely adopted frequency-domain method, harmonic balance (HB) provides efficient steady-state circuit analysis for analog and RF circuits. The conventional matrix-implicit Krylov subspace technique with the block-diagonal (BD) preconditioner has made it possible to compute the steady-state responses of large-scale circuits. However, not all HB problems, particularly strongly nonlinear circuit... View full abstract»

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  • Automatic Design Space Exploration of Register Bypasses in Embedded Processors

    Publication Year: 2007 , Page(s): 2102 - 2115
    Cited by:  Papers (5)
    Save to Project icon | Request Permissions | Click to expandAbstract | PDF file iconPDF (1293 KB) |  | HTML iconHTML  

    Register bypassing is a popular and powerful architectural feature to improve processor performance in pipelined processors by eliminating certain data hazards. However, extensive bypassing comes with a significant impact on cycle time, area, and power consumption of the processor. Recent research therefore advocates the use of partial bypassing in a processor. However, accurate performance evalua... View full abstract»

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  • A Piecewise-Linear Moment-Matching Approach to Parameterized Model-Order Reduction for Highly Nonlinear Systems

    Publication Year: 2007 , Page(s): 2116 - 2129
    Cited by:  Papers (20)
    Save to Project icon | Request Permissions | Click to expandAbstract | PDF file iconPDF (812 KB) |  | HTML iconHTML  

    This paper presents a parameterized reduction technique for highly nonlinear systems. In our approach, we first approximate the nonlinear system with a convex combination of parameterized linear models created by linearizing the nonlinear system at points along training trajectories. Each of these linear models is then projected using a moment-matching scheme into a low-order subspace, resulting i... View full abstract»

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  • BoxRouter: A New Global Router Based on Box Expansion and Progressive ILP

    Publication Year: 2007 , Page(s): 2130 - 2143
    Cited by:  Papers (6)  |  Patents (1)
    Save to Project icon | Request Permissions | Click to expandAbstract | PDF file iconPDF (1030 KB) |  | HTML iconHTML  

    In this paper, we propose a new global router, BoxRouter, powered by the concept of box expansion, progressive integer linear programming (PILP), and adaptive maze routing (AMR). BoxRouter first uses a simple prerouting strategy to predict and capture the most congested region with high fidelity as compared to the final routing. Based on progressive box expansion initiated from the most congested ... View full abstract»

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  • Detailed Placement for Enhanced Control of Resist and Etch CDs

    Publication Year: 2007 , Page(s): 2144 - 2157
    Cited by:  Papers (4)  |  Patents (2)
    Save to Project icon | Request Permissions | Click to expandAbstract | PDF file iconPDF (1232 KB) |  | HTML iconHTML  

    Subresolution assist feature (SRAF) and etch-dummy-insertion techniques have been absolutely essential for process-window enhancement and CD control in photo and etch processes. However, as focus levels change during lithography manufacturing, CDs at a given ldquolegalrdquo pitch can fail to achieve manufacturing tolerances. Placed standard-cell layouts may not have the ideal whitespace distributi... View full abstract»

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  • Diffusion-Based Placement Migration With Application on Legalization

    Publication Year: 2007 , Page(s): 2158 - 2172
    Cited by:  Patents (3)
    Save to Project icon | Request Permissions | Click to expandAbstract | PDF file iconPDF (867 KB) |  | HTML iconHTML  

    Placement migration is the movement of cells within an existing placement to address a variety of postplacement design-closure issues, such as timing, routing congestion, signal integrity, and heat distribution. To fix a design problem, one would like to perturb the design as little as possible while preserving the integrity of the original placement. This paper presents a new diffusion-based plac... View full abstract»

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  • ECO-System: Embracing the Change in Placement

    Publication Year: 2007 , Page(s): 2173 - 2185
    Cited by:  Papers (3)  |  Patents (2)
    Save to Project icon | Request Permissions | Click to expandAbstract | PDF file iconPDF (1016 KB) |  | HTML iconHTML  

    In a realistic design flow, circuit and system optimizations must interact with physical aspects of the design. For example, improvements in timing and power may require the replacement of large modules with variants that have different power/delay tradeoff, shape, and connectivity. New logic may be added late in the design flow, which is subject to interconnect optimization. To support such flexi... View full abstract»

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  • Fast and Accurate Cosimulation of MPSoC Using Trace-Driven Virtual Synchronization

    Publication Year: 2007 , Page(s): 2186 - 2200
    Cited by:  Papers (11)  |  Patents (1)
    Save to Project icon | Request Permissions | Click to expandAbstract | PDF file iconPDF (1218 KB) |  | HTML iconHTML  

    As MPSoC has become an effective solution to ever-increasing design complexity of modern embedded systems, fast and accurate cosimulation of such systems is becoming a tough challenge. Cosimulation performance is in inverse proportion to the number of processor simulators in conventional cosimulation frameworks with lock-step synchronization schemes. To overcome this problem, we propose a novel ti... View full abstract»

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  • Testing Network-on-Chip Communication Fabrics

    Publication Year: 2007 , Page(s): 2201 - 2214
    Cited by:  Papers (13)
    Save to Project icon | Request Permissions | Click to expandAbstract | PDF file iconPDF (614 KB) |  | HTML iconHTML  

    Network-on-chip (NoC) communication fabrics will be increasingly used in many large multicore system-on-chip designs in the near future. A relevant challenge that arises from this trend is that the test costs associated with NoC infrastructures may account for a significant part of the total test budget. In this paper, we present a novel methodology for testing such NoC architectures. The proposed... View full abstract»

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  • Delay Fault Coverage Enhancement by Partial Clocking for Low-Power Designs With Heavily Gated Clocks

    Publication Year: 2007 , Page(s): 2215 - 2221
    Cited by:  Papers (2)
    Save to Project icon | Request Permissions | Click to expandAbstract | PDF file iconPDF (342 KB) |  | HTML iconHTML  

    Testing for delay faults in heavily gated clock designs has the major test challenges of reduced fault coverage and high test power consumption. In the scan-test method, gated clocks are often simplified and replaced with global test clocks. As such, partial clocking by the gated clocks is not inherited in test operations. Global clocking suffers from delay fault coverage loss because a sensitizat... View full abstract»

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  • A Bus-Encoding Scheme for Crosstalk Elimination in High-Performance Processor Design

    Publication Year: 2007 , Page(s): 2222 - 2227
    Cited by:  Papers (5)
    Save to Project icon | Request Permissions | Click to expandAbstract | PDF file iconPDF (234 KB) |  | HTML iconHTML  

    A crosstalk effect leads to increases in delay and power consumption and, in the worst-case scenario, to inaccurate results. With the scale down of technology to deep-submicrometer level, the crosstalk effect between adjacent wires becomes more and more serious, particularly between long on-chip buses. In this paper, we propose a deassembler/assembler technique to eliminate undesirable crosstalk e... View full abstract»

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  • IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems Information for authors

    Publication Year: 2007 , Page(s): 2228
    Save to Project icon | Request Permissions | PDF file iconPDF (24 KB)  
    Freely Available from IEEE
  • 2007 Index IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems Vol. 26

    Publication Year: 2007 , Page(s): 2229 - 2256
    Save to Project icon | Request Permissions | PDF file iconPDF (329 KB)  
    Freely Available from IEEE
  • IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems society information

    Publication Year: 2007 , Page(s): C3
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    Freely Available from IEEE

Aims & Scope

The purpose of this Transactions is to publish papers of interest to individuals in the areas of computer-aided design of integrated circuits and systems.

Full Aims & Scope

Meet Our Editors

Editor-in-Chief

VIJAYKRISHNAN NARAYANAN
Pennsylvania State University
Dept. of Computer Science. and Engineering
354D IST Building
University Park, PA 16802, USA
vijay@cse.psu.edu