# IEEE Journal of Solid-State Circuits

### Early Access Articles

Early Access articles are made available in advance of the final electronic or print versions. Early Access articles are peer reviewed but may not be fully edited. They are fully citable from the moment they appear in IEEE Xplore.

## Filter Results

Displaying Results 1 - 25 of 50
• ### A Stacked CMOS Image Sensor With Array-Parallel ADC Architecture

Publication Year: 2018, Page(s):1 - 10
| |PDF (6460 KB)

This paper presents a 4.1 megapixel, 280 frames/s, back-illuminated, stacked, global shutter (GS) CMOS image sensor with array-parallel analog-to-digital converter (ADC) architecture for region-control applications. The sensor solves an image distortion problem caused by rolling shutter in a pixel sub-array by utilizing a floating diffusion (FD) memory to implement GS operation. A newly developed ... View full abstract»

• ### 0.04-mm² 103-dB-A Dynamic Range Second-Order VCO-Based Audio Σ Δ ADC in 0.13-μm CMOS

Publication Year: 2018, Page(s):1 - 12
| |PDF (3721 KB)

This paper presents a compact-area, low-power, highly digital analog-to-digital converter (ADC) for audio applications. The proposed converter is implemented using only oscillators and digital circuitry, without operational amplifiers nor other highly linear circuits. The ADC consists of two twin second-order ΣΔ modulators, which can work both individually or in a pseudodifferential ... View full abstract»

• ### A Hysteretic Buck Converter With 92.1% Maximum Efficiency Designed for Ultra-Low Power and Fast Wake-Up SoC Applications

Publication Year: 2018, Page(s):1 - 13
| |PDF (6448 KB)

This paper presents a dc-dc converter for integration in the power management unit of an ultra-low power microcontroller. The converter is designed to significantly reduce the wake-up energy and startup delay of the supplied core. The use of a minimized output capacitor is the key factor to save the wake-up energy. The converter is buffered with only 56 nF and guarantees a stable output of 1.2 V w... View full abstract»

• ### An Interferer-Tolerant CMOS Code-Domain Receiver Based on N-Path Filters

Publication Year: 2018, Page(s):1 - 11
| |PDF (3656 KB)

This paper extends N-path filtering to the code domain by proposing code-modulated local oscillator signals. A correlator-based perspective of N-path mixer receiver (RX) is presented to demonstrate interferer-rejection and desired signal reception in a code-domain N-path RX. Pairs of Walsh-function-based codes are proposed for modulating desired RX and known interferers [such as self-interference ... View full abstract»

• ### A 50-Gb/s High-Sensitivity (-9.2 dBm) Low-Power (7.9 pJ/bit) Optical Receiver Based on 0.18-μm SiGe BiCMOS Technology

Publication Year: 2018, Page(s):1 - 21
| |PDF (6859 KB)

A 50-Gb/s optical receiver (RX) based on 0.18-μm SiGe BiCMOS technology was fabricated and evaluated. To improve the horizontal eye opening and sensitivity of the RX without degrading its power efficiency, it is configured with a two-stage pre-amplifier with high gain (56 dBΩ) and high bandwidth (35 GHz), a high-accuracy automatic decision-threshold control (ATC) consisting of power-... View full abstract»

• ### Analysis and Design of a 30- to 220-GHz Balanced Cascaded Single-Stage Distributed Amplifier in 130-nm SiGe BiCMOS

Publication Year: 2018, Page(s):1 - 11
| |PDF (3655 KB)

This paper describes a novel distributed amplifier (DA) architecture for ultra-wide band of operation at millimeter-wave frequency. The DA consists of two cascaded single-stage DAs (CSSDAs) embedded in a balanced architecture. The implemented design retains the benefits of CSSDAs in terms of high maximum frequency, broad band of operation, and compact area, while significantly improving the amplif... View full abstract»

• ### A 2.4-GHz RF Fractional-N Synthesizer With BW = 0.25fREF

Publication Year: 2018, Page(s):1 - 12
| |PDF (3487 KB)

A fractional-N synthesizer architecture incorporates a 35-tap finite impulse response filter that suppresses the ΣΔ noise, but does not affect the loop bandwidth (BW). Employing a three-stage ring oscillator and operating with a 22.6-MHz reference frequency, the synthesizer achieves a BW of around 5.6 MHz with a power consumption of 10 mW. Realized in 45-nm digital CMOS technology, t... View full abstract»

• ### A 60-Gb/s 1.9-pJ/bit NRZ Optical Receiver With Low-Latency Digital CDR in 14-nm CMOS FinFET

Publication Year: 2018, Page(s):1 - 11
| |PDF (7667 KB)

This paper presents an analysis on the loop dynamics of the digital clock and data recovery (CDR) circuits and the design details of a non-return to zero optical receiver (RX) in a 14-nm bulk CMOS finFET technology with high jitter tolerance (JTOL) performance, which is designed based on the analysis. The digital CDR logic is designed full custom in order to keep it running at a quarter rate clock... View full abstract»

• ### Enhanced-Selectivity High-Linearity Low-Noise Mixer-First Receiver With Complex Pole Pair Due to Capacitive Positive Feedback

Publication Year: 2018, Page(s):1 - 13
| |PDF (4540 KB)

A mixer-first receiver (RX) with enhanced selectivity and high dynamic range is proposed, targeting to remove surface acoustic-wave-filters in mobile phones and cover all frequency bands up to 6 GHz. Capacitive negative feedback across the baseband (BB) amplifier serves as a blocker bypassing path, while an extra capacitive positive feedback path offers further blocker rejection. This combination ... View full abstract»

• ### Recryptor: A Reconfigurable Cryptographic Cortex-M0 Processor With In-Memory and Near-Memory Computing for IoT Security

Publication Year: 2018, Page(s):1 - 11
| |PDF (4501 KB)

Providing security for the Internet of Things (IoT) is increasingly important, but supporting many different cryptographic algorithms and standards within the physical constraints of IoT devices is highly challenging. Software implementations are inefficient due to the high bitwidth cryptographic operations; domain-specific accelerators are often inflexible; and reconfigurable crypto processors ge... View full abstract»

• ### A 69-dB SNDR 300-MS/s Two-Time Interleaved Pipelined SAR ADC in 16-nm CMOS FinFET With Capacitive Reference Stabilization

Publication Year: 2018, Page(s):1 - 11
| |PDF (3216 KB)

A two-time interleaved pipelined SAR ADC in 16-nm CMOS achieving 11.2-bit ENOB at 300 MS/s is presented. To cancel the signal-dependent voltage ripple on the reference node due to DAC switching, it employs a stabilization scheme based on the use of auxiliary DACs. The charge drawn from the reference becomes signal-independent, greatly reducing the requirements for the reference decoupling capacita... View full abstract»

• ### A Fully On-Chip 80-pJ/b OOK Super-Regenerative Receiver With Sensitivity-Data Rate Tradeoff Capability

Publication Year: 2018, Page(s):1 - 14
| |PDF (2983 KB)

This paper presents an ultra-low power super-regenerative receiver suitable for ON-OFF keying modulation and provides analytical insight into its design procedure. The receiver is fabricated in 40-nm CMOS technology and operates in the ISM band of 902-928 MHz. Binary search algorithm through successive approximation register architecture is being exploited to calibrate the internally generated que... View full abstract»

• ### Precision Passive-Charge-Sharing SAR ADC: Analysis, Design, and Measurement Results

Publication Year: 2018, Page(s):1 - 12
| |PDF (4291 KB)

This paper presents a passive-charge-sharing successive approximation register (SAR) analog-to-digital converter (ADC) that achieves 16-bit linearity. It is known that on-chip passive charge sharing suffers from poor linearity due to the unregulated reference voltage during bit trials. This paper gives a detailed analysis for the reasons of poor linearity for passive-charge-sharing SAR ADCs and pr... View full abstract»

• ### A 25-30 GHz Fully-Connected Hybrid Beamforming Receiver for MIMO Communication

Publication Year: 2018, Page(s):1 - 13
| |PDF (9649 KB)

This paper presents a fully-connected' hybrid beamforming receiver that independently weights each element in an antenna array prior to separate downconversion chains that output independent baseband streams. A receiver architecture is introduced, which implements RF-domain complex-valued Cartesian weighting, RF-domain combining, and multi-stream heterodyne complex-quadrature downconversion. Eac... View full abstract»

• ### Asynchronous Approximation of a Center of Gravity for Pixel Detectors' Readout Circuits

Publication Year: 2018, Page(s):1 - 9
| |PDF (4043 KB)

This paper presents an implementation of asynchronous approximation of a center of gravity of a binary object on a focal plane of a pixel detector. The direct field of its application is dealing with charge sharing in processing of signals from semiconductor X-ray hybrid pixel detectors. The developed algorithm is called the center of gravity in a temporal object (COGITO), standing for approximati... View full abstract»

• ### A Low-Cost Scalable 32-Element 28-GHz Phased Array Transceiver for 5G Communication Links Based on a 2x2 Beamformer Flip-Chip Unit Cell

Publication Year: 2018, Page(s):1 - 15;
| |PDF (6470 KB)

This paper presents a scalable 28-GHz phased-array architecture suitable for fifth-generation (5G) communication links based on four-channel (2x2) transmit/receive (TRX) quad-core chips in SiGe BiCMOS with flip-chip packaging. Each channel of the quad-core beamformer chip has 4.6-dB noise figure (NF) in the receive (RX) mode and 10.5-dBm output 1-dB compression point (OP1dB) in the transmit (TX) m... View full abstract»

• ### Analysis and Design of a 20-MHz Bandwidth, 50.5-dBm OOB-IIP3, and 5.4-mW TIA for SAW-Less Receivers

Publication Year: 2018, Page(s):1 - 13
| |PDF (5431 KB)

A power-efficient transimpedance amplifier with wide channel bandwidth is proposed to meet the stringent linearity requirements of surface acoustic wave-less frequency-division duplexing receivers. A unity-gain loop bandwidth of 1.6 GHz is achieved with low-power dissipation. This was done without using any internal compensation but relying on zeros, both within the operational transconductance am... View full abstract»

• ### A 10-bit 2.6-GS/s Time-Interleaved SAR ADC With a Digital-Mixing Timing-Skew Calibration Technique

Publication Year: 2018, Page(s):1 - 10
| |PDF (2802 KB)

A 16-channel time-interleaved 10-bit SAR analog-to-digital converter (ADC), employing the proposed delta-sampling auxiliary SAR ADCs and a digital-mixing calibration technique to compensate timing-skew error, achieves a 2.6-GS/s sampling rate. The ADC has been fabricated in a 40-nm CMOS technology and achieves a 50.6-dB signal-to-noise-and-distortion ratio at Nyquist rate while dissipating 18.4 mW... View full abstract»

• ### A CMOS Timer-Injector Integrated Circuit for Self-Powered Sensing of Time-of-Occurrence

Publication Year: 2018, Page(s):1 - 11
| |PDF (3518 KB)

Self-powered sensing of the time-of-occurrence of an event is challenging, because it requires access to a reliable time reference or a synchronized clock. In this paper, we propose for the first time a self-powered integrated circuit that is capable of time-stamping asynchronous mechanical events of interest. The core of the proposed design is the integration of two self-powered modules: 1) a chi... View full abstract»

• ### A SAW-Less Tunable RF Front End for FDD and IBFD Combining an Electrical-Balance Duplexer and a Switched-LC N-Path LNA

Publication Year: 2018, Page(s):1 - 12
| |PDF (3877 KB)

This paper proposes a surface-acoustic wave (SAW)-less tunable RF front end (RF-FE) using an electrical-balance duplexer (EBD) integrated with a switched-LC N-path low-noise amplifier (LNA). The EBD cancels the transmitter-receiver (TX-RX) leakage at the RX frequency by dynamically optimizing the balance of a hybrid transformer, which enables in-band full-duplex (IBFD) operation. A transconductor-... View full abstract»

• ### A 16-Element 4-Beam 1 GHz IF 100 MHz Bandwidth Interleaved Bit Stream Digital Beamformer in 40 nm CMOS

Publication Year: 2018, Page(s):1 - 11
| |PDF (3648 KB)

A 1 GHz intermediate frequency, 16-element, 4-beam digital beamformer facilitates multi-in multi-out, 5G mobile, and other emerging communication standards. Digital beamforming has been limited by high power consumption, large die area, and the need for a large number of analog-to-digital converters (ADCs). The proposed digital beamformer addresses these issues by combining interleaved bit stream ... View full abstract»

• ### 320 x 240 Back-Illuminated 10-μm CAPD Pixels for High-Speed Modulation Time-of-Flight CMOS Image Sensor

Publication Year: 2018, Page(s):1 - 8
| |PDF (4505 KB)

A 320x240 back-illuminated (BI) time-of-flight CMOS image sensor with 10-μm current-assisted photonic demodulator (CAPD) pixels has been developed. The BI pixel structure maximizes fill factor, allows for flexible transistor positioning, and makes the light path independent of the metal layers. The BI-CAPD pixel, which has relatively thinner substrate than that of front-illuminated CAPD, ma... View full abstract»

• ### Outphasing Class-E Power Amplifiers: From Theory to Back-Off Efficiency Improvement

Publication Year: 2018, Page(s):1 - 13
| |PDF (6500 KB)

This paper presents an analysis of outphasing class-E power amplifiers (OEPAs), using load-pull analyses of single class-E PAs. This analysis is subsequently used to rotate and shift power contours and rotate the efficiency contours to improve the efficiency of OEPAs at deep power back-off, to improve the output power dynamic range (OPDR), and to reduce switch voltage stress. To validate the theor... View full abstract»

• ### Dynamic Power Reduction in Scalable Neural Recording Interface Using Spatiotemporal Correlation and Temporal Sparsity of Neural Signals

Publication Year: 2018, Page(s):1 - 13
| |PDF (5909 KB)

We report a scalable neural recording interface with embedded lossless compression to reduce dynamic power consumption (PD) for data transmission in high-density neural recording systems. We investigated the characteristics of neural signals and implemented effective lossless compression for local field potential (LFP) and extracellular action potential (EAP or spike) in separate signal paths. For... View full abstract»

• ### Frequency and Power Scaling in mm-Wave Colpitts Oscillators

Publication Year: 2018, Page(s):1 - 10
| |PDF (3348 KB)

The maximum oscillation frequency depends on the oscillator topology and the loss of oscillator's active and passive components. The oscillator phase noise, and hence the oscillator figure-of-merit (FOM), degrades much faster than the well-known low-frequency expressions as the oscillation frequency reaches the maximum oscillation frequency. This paper covers the analysis and design of Colpitts os... View full abstract»

## Aims & Scope

The IEEE Journal of Solid-State Circuits publishes papers each month in the broad area of solid-state circuits with particular emphasis on transistor-level design of integrated circuits.

Full Aims & Scope

## Meet Our Editors

Editor-in-Chief

Jan Craninckx
Imec
Kapeldreef 75
B-3001 Leuven, Belgium
jssc.craninckx@gmail.com