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# IEEE Transactions on Very Large Scale Integration (VLSI) Systems

### Early Access Articles

Early Access articles are made available in advance of the final electronic or print versions. Early Access articles are peer reviewed but may not be fully edited. They are fully citable from the moment they appear in IEEE Xplore.

## Filter Results

Displaying Results 1 - 25 of 62
• ### A 1-Gb/s 6-10-GHz, Filterless, Pulsed UWB Transmitter With Symmetrical Waveform Analysis and Generation

Publication Year: 2018, Page(s):1 - 12
| | PDF (6424 KB)

This paper presents a fully integrated, regulation-aware pulsed ultra wideband (UWB) transmitter (TX) for low-cost, high-data-rate applications. Waveform nonidealities have been systematically analyzed for the first time, demonstrating that envelope asymmetry may cause spectrum regulation violations. In order to generate regulation-compliant UWB pulses without costly filters, the proposed high-dat... View full abstract»

• ### Offset-Compensated High-Speed Sense Amplifier for STT-MRAMs

Publication Year: 2018, Page(s):1 - 8
| | PDF (3218 KB)

Spin-transfer torque magnetic random access memory (STT-MRAM) has emerged as a promising candidate for next generation computing systems. However, with increasing process variation and decreasing supply voltage, a big design challenge of embedded STT-MRAMs is to guarantee negligible read disturbance and high yield. To deal with the read reliability challenge, an offset compensated, high-speed sens... View full abstract»

• ### Accelerating k-Medians Clustering Using a Novel 4T-4R RRAM Cell

Publication Year: 2018, Page(s):1 - 14
| | PDF (4178 KB)

Clustering is a crucial tool for analyzing data in virtually every scientific and engineering discipline. The U.S. National Academy of Sciences has recently announced the seven giants of statistical data analysis' in which data clustering plays a central role. This report also emphasizes that more scalable solutions are required to enable time and space clustering for the future large-scale data... View full abstract»

• ### Energy-Efficient Pedestrian Detection System: Exploiting Statistical Error Compensation for Lossy Memory Data Compression

Publication Year: 2018, Page(s):1 - 11
| | PDF (3105 KB)

Pedestrian detection represents an important application for embedded vision systems. Focusing on the most energy constrained implementations, systems have typically employed histogram of oriented gradients features and support vector machine classification, which leads to low detection accuracy (a log-average miss rate of 68% on the Caltech Pedestrian dataset). Additionally, single-scale d... View full abstract»

• ### Efficient Spectrum Sensing for Aeronautical LDACS Using Low-Power Correlators

Publication Year: 2018, Page(s):1 - 9
| | PDF (2767 KB)

Air traffic has seen tremendous growth over the past decade pushing the need for enhanced air traffic management schemes. The $L$-band digital aeronautical communication system (LDACS) is gaining traction as a scheme of choice, and aims to exploit the capabilities of modern digital communication techniques and computing architectures. Cognitive radio-based approaches have also been proposed for LD... View full abstract»

• ### Clocked Hysteresis Control Scheme With Power-Law Frequency Scaling in Buck Converter to Improve Light-Load Efficiency for IoT Sensor Nodes

Publication Year: 2018, Page(s):1 - 12
| | PDF (2958 KB)

A clocked hysteresis control scheme with power-law frequency scaling is proposed to improve the conversion efficiency at a light load current, and it is applied to a buck converter design. By replacing a continuously on comparator used in conventional hysteresis control by a clocked comparator with power-law frequency scaling, the buck converter consumes no direct current (dc) in the comparators. ... View full abstract»

• ### DVFT: A Lightweight Solution for Power-Supply Noise-Based TRNG Using Dynamic Voltage Feedback Tuning System

Publication Year: 2018, Page(s):1 - 14
| | PDF (2472 KB)

True random number generators (TRNGs) are central to many computing applications, particularly in security domains such as cryptography. In this paper, we consider the design and implementation of a low-cost and lightweight TRNG. In the interest of being thorough, we examined six different power supplies in order to verify the noncyclostationary behavior of the voltage sources. Our novel TRNG mode... View full abstract»

• ### A Reliable Strong PUF Based on Switched-Capacitor Circuit

Publication Year: 2018, Page(s):1 - 11
| | PDF (2124 KB)

This paper presents a highly reliable and invasive-attack-resistant switched-capacitor (SC) strong physical unclonable function (PUF), which can offer an extremely large number of challenge-response pairs. Two symmetrical capacitor arrays that are controlled by challenges are used to realize the strong ability of SC PUF. The mismatch created by the capacitor arrays in real fabrication is sampled b... View full abstract»

• ### Performance and Energy-Efficient Design of STT-RAM Last-Level Cache

Publication Year: 2018, Page(s):1 - 14
| | PDF (4833 KB)

Recent research has proposed having a die-stacked last-level cache (LLC) to overcome the memory wall. Lately, spin-transfer-torque random access memory (STT-RAM) caches have received attention, since they provide improved energy efficiency compared with DRAM caches. However, recently proposed STT-RAM cache architectures unnecessarily dissipate energy by fetching unneeded cache lines (CLs) into the... View full abstract»

• ### Contactless Testing for Prebond Interposers

Publication Year: 2018, Page(s):1 - 10
| | PDF (2166 KB)

Interposers play an important role in integrating multiple dies in a staked-die product. Prebond testing of interposers is an essential process for improving production yield. However, the traditional testing mechanism via probing is not appropriate, since it could destroy the fragile interposers. To this end, we propose a contactless testing methodology for prebond interposers. The testing method... View full abstract»

• ### Experimental Investigation of 4-kb RRAM Arrays Programming Conditions Suitable for TCAM

Publication Year: 2018, Page(s):1 - 9
| | PDF (4465 KB)

Resistive random access memories (RRAMs) feature high-speed operations, low-power consumption, and nonvolatile retention, thus serving as a promising candidate for future memory applications. To explore the applications of the RRAM, switching variability and cycling endurance need to be addressed. This paper presents extensive characterizations of multi-kb RRAM arrays during forming, set, reset, a... View full abstract»

• ### A Design of Fast-Settling, Low-Power 4.19-MHz Real-Time Clock Generator With Temperature Compensation and 15-dB Noise Reduction

Publication Year: 2018, Page(s):1 - 8
| | PDF (3002 KB)

This paper presents a fast-settling, low-power, low-noise real-time clock (RTC) generator for a 4.194304-MHz crystal oscillator. The fast settling reduces the startup time of the proposed RTC generator using a negative transcondutance booster and a crystal energy booster. The low power is only operated to reduce the total power consumption in the standby mode with the use of a peak-and-low detecto... View full abstract»

• ### A Balunless Frequency Multiplier With Differential Output by Current Flow Manipulation

Publication Year: 2018, Page(s):1 - 12
| | PDF (3078 KB)

A balunless frequency doubler (FD) architecture which can provide differential output without any additional balun required is proposed in this paper. The architecture manipulates the desired second-harmonic currents around the doubler core by a multifunction network to avoid any leakage current path from the output current loop. Therefore, the output currents extracted from the same current loop ... View full abstract»

• ### Reliability-Aware Test Methodology for Detecting Short-Channel Faults in On-Chip Networks

Publication Year: 2018, Page(s):1 - 14
| | PDF (3762 KB)

With the advent of rapidly evolving nanoelectronic systems, compact implementation of versatile and dense network-on-chips (NoCs) on a die has emerged as technology-of-choice for multicore computing. However, because of the increased density, NoCs often suffer from various types of manufacturing faults, which degrade the yield and jeopardize the reliability of the overall system. For example, shor... View full abstract»

• ### A Simple Yet Efficient Accuracy-Configurable Adder Design

Publication Year: 2018, Page(s):1 - 14
| | PDF (8607 KB)

Approximate computing is a promising approach for low-power IC design and has recently received considerable research attention. To accommodate dynamic levels of approximation, a few accuracy-configurable adder (ACA) designs have been developed in the past. However, these designs tend to incur large area overheads as they rely on either redundant computing or complicated carry prediction. Some of ... View full abstract»

• ### A Fully Synthesized 77-dB SFDR Reprogrammable SRMC Filter Using Digital Standard Cells

Publication Year: 2018, Page(s):1 - 13
| | PDF (4109 KB)

This paper presents a fully synthesized 0.4-V analog biquad filter in a 0.13-μm CMOS technology using digital standard cells. In contrast to a custom-designed inverter-based amplifier in the conventional design, a new NAND-/NOR-gate-based microoperational amplifier (uOP) operating in weak inversion is proposed in this paper. Furthermore, by employing feedforward compensation for loop stabil... View full abstract»

• ### A 128-Tap Highly Tunable CMOS IF Finite Impulse Response Filter for Pulsed Radar Applications

Publication Year: 2018, Page(s):1 - 12
| | PDF (2609 KB)

A configurable-bandwidth (BW) filter is presented in this paper for pulsed radar applications. To eliminate dispersion effects in the received waveform, a finite impulse response (FIR) topology is proposed, which has a measured standard deviation of an in-band group delay of 11 ns that is primarily dominated by the inherent, fully predictable delay introduced by the sample-and-hold. The filter ope... View full abstract»

• ### VOSsim: A Framework for Enabling Fast Voltage Overscaling Simulation for Approximate Computing Circuits

Publication Year: 2018, Page(s):1 - 5
| | PDF (1214 KB)

Approximate computing emerges as a new design paradigm for generating energy-efficient computing systems. Voltage overscaling (VOS) forms a very promising technique to generate approximate circuits, and its application in cooperation to other approximate techniques is proven to lead to more efficient solutions. However, the existing design tools fail to provide effective voltage-aware simulation f... View full abstract»

• ### Fast Electromigration Stress Evolution Analysis for Interconnect Trees Using Krylov Subspace Method

Publication Year: 2018, Page(s):1 - 12
| | PDF (2519 KB)

Electromigration effects are a key failure mechanism for copper-based dual damascene interconnects wires in semiconductor technologies. However, accurately predicting the time-to-failure for a complicated interconnect tree in a VLSI interconnect layout requires detailed knowledge of the stress evolutions over time, and is subject to time-varying currents and temperature. This is a challenging prob... View full abstract»

Publication Year: 2018, Page(s):1 - 11
| | PDF (4191 KB)

In this paper, we propose a novel memory architecture with the capability of single-cycle row-wise/column-wise accesses. Such an architecture is highly suitable for workloads featuring spatial locality in multiple dimensions, which is a characteristic of many matrix and array operations. We describe in detail the circuit design techniques enabling the proposed architectures, as well as the viabili... View full abstract»

• ### Aging Management Using a Reconfigurable Switch Network for Arrays of Nonideal Power Cells

Publication Year: 2018, Page(s):1 - 12
| | PDF (3834 KB)

Power cells, such as battery cells, solar cells, and fuel cells, are often connected in series and parallel to satisfy a desired amount of power and energy density as well as the terminal voltage. However, it is allowed to compose an array of power cells only when the individual cell has the identical characteristics among each other. However, even originally identical cells eventually have differ... View full abstract»

• ### Toward an Energy-Efficient High-Voltage Compliant Visual Intracortical Multichannel Stimulator

Publication Year: 2018, Page(s):1 - 14
| | PDF (8312 KB)

We present, in this paper, a new multichip system aimed toward building an implantable visual intracortical stimulation device. The objective is to deliver energy-optimum pulse patterns to neural sites with needed compliance voltage across high electrode-tissue interface impedance of implantable microelectrodes. The first chip is an energy-efficient stimuli generator (SG), and the second one is a ... View full abstract»

• ### Performance Evaluation and Optimization of HBM-Enabled GPU for Data-Intensive Applications

Publication Year: 2018, Page(s):1 - 10
| | PDF (1912 KB)

Graphics processing units (GPUs) are widely used to accelerate data-intensive applications. To improve the performance of data-intensive applications, higher GPU memory bandwidth is desirable. Traditional graphics double data rate memories achieve higher bandwidth by increasing frequency, which leads to excessive power consumption. Recently, a new memory technology called high-bandwidth memory (HB... View full abstract»

• ### A 2M1M Crossbar Architecture: Memory

Publication Year: 2018, Page(s):1 - 11
| | PDF (2952 KB)

Memristor crossbar architectures are considered as one of the most promising platforms for future memory, logic, and in-memory computing applications. This paper presents a 2M1M crossbar architecture, capable of memory and logic applications, based on a transistor-less memory cell, which behaves as a switching circuit. The proposed memory cell consists of two access and one target memristors that ... View full abstract»

• ### All-Digital Process-Variation-Calibrated Timing Generator for ATE With 1.95-ps Resolution and Maximum 1.2-GHz Test Rate

Publication Year: 2018, Page(s):1 - 11
| | PDF (2263 KB)

In this paper, an all-digital process-variation-calibrated high-performance timing generator for an automatic test equipment is proposed. The proposed timing generator generates process-variation-tolerant variable delays for high and wide-range testing clock frequency. In order to increase the testing clock frequency, a channel of the proposed timing generator consists of four subtiming generators... View full abstract»

## Aims & Scope

Design and realization of microelectronic systems using VLSI/ULSI technologies requires close collaboration among scientists and engineers in the fields of systems architecture, logic and circuit design, chips and wafer fabrication, packaging, testing, and systems applications. Generation of specifications, design, and verification must be performed at all abstraction levels, including the system, register-transfer, logic, circuit, transistor, and process levels. To address this critical area through a common forum, the IEEE Transactions on VLSI Systems was founded.

Full Aims & Scope

## Meet Our Editors

Editor-in-Chief

Krishnendu Chakrabarty
Department of Electrical Engineering
Duke University
Durham, NC 27708 USA
Krish@duke.edu