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Circuits and Systems I: Regular Papers, IEEE Transactions on

Issue 10 • Date Oct. 2007

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Displaying Results 1 - 25 of 27
  • Table of contents

    Publication Year: 2007 , Page(s): C1 - C4
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  • IEEE Transactions on Circuits and Systems—I: Regular Papers publication information

    Publication Year: 2007 , Page(s): C2
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  • Pseudonoise Optical Modulation for Real-Time 3-D Imaging With Minimum Interference

    Publication Year: 2007 , Page(s): 2109 - 2119
    Cited by:  Papers (2)
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (566 KB) |  | HTML iconHTML  

    In optical time-of-flight (TOF) range imaging, harmonic intensity modulation of the illumination source is very common. By detecting the phase delay between emitted and reflected sinusoids, the distance can be measured accurately. However, this harmonic approach does not allow for the concurrent operation of several TOF range cameras because the arbitrary superposition of several differently parametrized sinusoids leads to a sinusoid with incorrect phase. To minimize inaccuracies by multi-camera interference (MCI), pseudonoise (PN) modulated intensity signals are employed for robust TOF range imaging. The time of flight is locally measured by correlating the incident light intensity with two time-shifted versions of the PN sequence, making use of smart demodulation pixels. We derive two fundamental expressions for the basic limitations of TOF measurements using PN sequences. Firstly, the precision of the distance measurement is limited by photon shot noise, and it essentially shows an inverse square root dependence of the number of detected photoelectrons. Secondly, MCI causes an inaccurate distance measurement given as the ratio of two sums. The denominator is the sum of two autocorrelation and two cross-correlation values; the nominator is the sum of one autocorrelation and one cross-correlation value. Due to the lack of a strict mathematical theory of correlation properties of m-sequences, an exhaustive numerical simulation was carried out to obtain expectation values of the distance measurement inaccuracy as a function of the sequence length and the number of interfering cameras. For experimental verification, an image sensor with 176 times 144 demodulation pixels was manufactured with a standard CMOS process offering a CCD option. Measurements taken with up to five concurrently operating sensors were in excellent agreement with our theoretical predictions concerning achievable distance accuracy. This confirms the aptness of PN techniques for multi-camera optica- l TOF range imaging. View full abstract»

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  • Development of Integrated Broad-Band CMOS Low-Noise Amplifiers

    Publication Year: 2007 , Page(s): 2120 - 2127
    Cited by:  Papers (21)
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (1021 KB) |  | HTML iconHTML  

    This paper presents a systematic design methodology for broad-band CMOS low-noise amplifiers (LNAs). The feedback technique is proposed to attain a better design tradeoff between gain and noise. The network synthesis is adopted for the implementation of broad-band matching networks. The sloped interstage matching is used for gain compensation. A fully integrated ultra-wide-band 0.18-mum CMOS LNA is developed following the design methodology. The measured noise figure is lower than 3.8 dB from 3 to 7.5 GHz, resulting in the excellent average noise figure of 3.48 dB. Operated on a 1.8-V supply, the LNA delivers 19.1-dB power gain and dissipates 32 mW of power. The gain-bandwidth product of the UWB LNA reaches 358 GHz, the record number for the 0.18-m CMOS broad-band amplifiers. The total chip size of the CMOS UWB LNA is 1.37 times 1.19 mm2. View full abstract»

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  • A 8-GHz SiGe HBT VCO Design on a Low Resistive Silicon Substrate Using GSML

    Publication Year: 2007 , Page(s): 2128 - 2136
    Cited by:  Papers (1)
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (1291 KB) |  | HTML iconHTML  

    A practical layout method called ground shield microstrip lines (GSML) is investigated for the reliable design of high frequency interconnection lines on a low resistive silicon substrate. GSML facilitates the prediction of parasitic networks at the expense of introducing negligible loss. The microwave performance of a GSML line structure is compared to that of a conventional metal line on the same standard silicon substrate (20 Omegamiddotcm). Then, the GSML structure is applied to an 8-GHz SiGe heterojunction bipolar transistor (HBT) voltage-controlled oscillator (VCO) circuit. The GSML method replaces the post layout simulation and reduces iteration time, increasing design efficiency. A fully integrated differential tuning SiGe HBT 8-GHz VCO is designed and tested. The measured phase noise for the VCO is dBc/Hz at 1-MHz offset with an output power of dBm. View full abstract»

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  • Modeling and Design of Multilevel Bang–Bang CDRs in the Presence of ISI and Noise

    Publication Year: 2007 , Page(s): 2137 - 2147
    Cited by:  Papers (10)
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (1152 KB) |  | HTML iconHTML  

    Multilevel clock-and-data recovery (CDR) systems are analyzed, modeled, and designed. A stochastic analysis provides probability density functions that are used to estimate the effect of intersymbol interference (ISI) and additive white noise on the characteristics of the phase detector (PD) in the CDR. A slope detector based novel multilevel bang-bang CDR architecture is proposed and modeled using the stochastic analysis and its performance compared with a typical multilevel Alexander PD-based CDR for equal-loop bandwidths. The rms jitter of the CDRs are predicted using a linear jitter model and a Markov chain and verified using behavioral simulations. Jitter tolerance simulations are also employed to compare the two CDRs. Both analytical calculations and behavioral simulations predict that at equal-loop bandwidths, the proposed architecture is superior to the Alexander type CDR at large ISI and low signal-to-noise ratios. View full abstract»

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  • An Analog Programmable Multidimensional Radial Basis Function Based Classifier

    Publication Year: 2007 , Page(s): 2148 - 2158
    Cited by:  Papers (13)  |  Patents (1)
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (2092 KB) |  | HTML iconHTML  

    A compact analog programmable multidimensional radial basis function (RBF)-based classifier is demonstrated. The probability distribution of each feature in the templates is modeled by a Gaussian function that is approximately realized by the bell-shaped transfer characteristics of a proposed floating-gate circuit, which we term a floating-gate bump circuit. The maximum likelihood, the mean, and the variance of the distribution are stored in floating-gate transistors and are independently programmable. By cascading these floating-gate bump circuits, the overall transfer characteristics approximate a multivariate Gaussian function with a diagonal covariance matrix. An array of these circuits constitute a compact multidimensional RBF-based classifier that can easily implement a Gaussian mixture model. When followed by a winner-take-all circuit, the RBF-based classifier forms an analog vector quantizer. We use receiver operating characteristic curves and equal error rate to evaluate the performance of our RBF-based classifier as well as a resultant analog vector quantizer. We show that the classifier performance is comparable to that of digital counterparts. The proposed approach can be at least two orders of magnitude more power efficient than the digital microprocessors at the same task. View full abstract»

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  • High-Voltage-Tolerant Analog Circuits Design in Deep-Submicrometer CMOS Technologies

    Publication Year: 2007 , Page(s): 2159 - 2166
    Cited by:  Papers (9)  |  Patents (2)
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (1124 KB) |  | HTML iconHTML  

    Electrical stress-relieved analog circuit design techniques using only baseline devices are presented, 1-to-2 logic level shifter, optional diode insertion, and adaptive biasing scheme are introduced to meet a reliability guideline that ensures sufficient lifetime. The proposed idea was successfully demonstrated with 12-bit I/Q digital-to-analog converter (DAC) and an operational amplifier having a Classs-AB output stage in 65-nm n-well CMOS technology and a high temperature operating life (HTOL) test was performed to evaluate the reliability of the design. View full abstract»

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  • A Low-Power, Compact, Adaptive Logarithmic Transimpedance Amplifier Operating Over Seven Decades of Current

    Publication Year: 2007 , Page(s): 2167 - 2177
    Cited by:  Papers (20)
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (1112 KB) |  | HTML iconHTML  

    This paper presents a detailed insight into the design space of wide-range transimpedance amplifiers enabling the design of micro-power, adaptive circuits for integrated current sensing applications. The analysis proves that the power dissipation of the nonadaptive structures varies linearly with dynamic range and quadratically with bandwidth. We present two adaptation techniques, modifying the bias current or output resistance, both of which alleviate this strong dependence on dynamic range. It is shown that adapting the bias current is most suitable for our application which requires a modest bandwidth but very wide dynamic range. Measurements demonstrate operation with currents ranging seven orders of magnitude from 200 fA to 2 muA with an average error of 0.8% and maximum error of 3.4%. The power consumption averaged over this entire range of currents is 3.45 muW . Either signal-to-noise ratio (SNR) or bandwidth can be made to tradeoff with the input current magnitude depending on the application. If the bandwidth is limited to 5 kHz, it achieves an average SNR of 65 dB. View full abstract»

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  • The Universal Circuit Simulator: A Mixed-Signal Approach to n-Port Network and Impedance Synthesis

    Publication Year: 2007 , Page(s): 2178 - 2183
    Cited by:  Papers (4)
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (687 KB) |  | HTML iconHTML  

    A mixed-signal universal architecture able to emulate the behavior of an n-port analog circuit is presented. It exploits second-generation current conveyors as analog input/output blocks and a field programmable gate array circuit as digital processing element. A prototype is also discussed for the specific case of a two-port network synthesis and experimental results in agreement with expected ones are provided. View full abstract»

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  • Fundamental Limitations of Continuous-Time Delta–Sigma Modulators Due to Clock Jitter

    Publication Year: 2007 , Page(s): 2184 - 2194
    Cited by:  Papers (30)
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (645 KB) |  | HTML iconHTML  

    We examine noise due to clock jitter in single-loop low-pass continuous-time delta-sigma (Delta Sigma) modulators (CT-DSMs) employing nonreturn to zero (NRZ) feedback digital-to-analog converters (DACs). Using the discrete-time version of the Bode sensitivity integral, we derive a lower bound on jitter noise and its relationship to the noise transfer function (NTF) of the modulator. We show that NTFs with optimized zeros result in lower jitter noise than those with all zeros at the origin. We give intuition to a recent observation (arrived through numerical optimization) that NTFs with peaking in their passbands have lower jitter noise than maximally flat NTFs. We propose a design procedure that minimizes the sum of the quantization and jitter noise. The arguments regarding Delta Sigma analog-to-digital converters are extended to Delta Sigma DACs and measurement results are presented. View full abstract»

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  • Analytical Synthesis of Current-Mode High-Order Single-Ended-Input OTA and Equal-Capacitor Elliptic Filter Structures With the Minimum Number of Components

    Publication Year: 2007 , Page(s): 2195 - 2210
    Cited by:  Papers (33)
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (1966 KB) |  | HTML iconHTML  

    None of the previously reported third-order and fourth-order operational transconductance amplifier and capacitor (OTA-C) elliptic filter structures use the minimum number of active and passive components. After an innovative algebraic decomposition for a complicated transfer function, i.e., a new analytical synthesis method, a current-mode odd-nth-order and a current-mode even-nth-order OTA-C elliptic filter structure having the following advantages are presented: 1) all the OTAs have single-ended inputs; 2) all the capacitors are grounded; 3) the minimum active and passive components are used. An equal-capacitance-type structure is designed taking into account the difficulty of precisely fabricating capacitances in integrated circuits. Although the above three advantages lead to the lowest total parasitics and to the most precise output response, the small deviations (such as the 3.5159% error in fp) of the four parameters of the new third-order OTA-C elliptic filter can be drastically reduced (for example, to 0.1553% error in fp) by only slightly tuning the four transconductances, but fixing the ratio of the given three capacitances, and without adding any other active and passive components. H-spice high-pass and low-pass simulations with 0.35-mum process are provided to demonstrate the theoretical results. View full abstract»

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  • A Wide-Band Power-Efficient Inductive Wireless Link for Implantable Microelectronic Devices Using Multiple Carriers

    Publication Year: 2007 , Page(s): 2211 - 2221
    Cited by:  Papers (65)  |  Patents (5)
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (2376 KB) |  | HTML iconHTML  

    This paper presents a novel inductive link for wireless transmission of power and data to biomedical implantable microelectronic devices using multiple carrier signals. Achieving higher data bandwidth without compromising the power efficiency is the driving force behind using multiple separate carriers. Two separate pairs of coils have been utilized for inductive power and forward data transmission, plus a pair of miniature antennas for back telemetry. One major challenge, however, is to minimize the interference among these carriers especially on the implantable side, where size and power are highly limited. Planar power coils with spiral shape are optimized in geometry to provide maximum coupling coefficient k. The data coils are designed rectangular in shape and wound across the power coils diameter to be oriented perpendicular to the power coil planes. The goal is to maximize data coils direct coupling, while minimize their cross-coupling with the power coils. The effects of coils geometry, orientation, relative distance, and misalignments on the coupling coefficients have been modeled and experimentally evaluated. View full abstract»

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  • Multitone Feedback Through Demodulating Log Detector for Detection of Spurious Emissions in Software Radio

    Publication Year: 2007 , Page(s): 2222 - 2228
    Cited by:  Papers (2)
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (381 KB) |  | HTML iconHTML  

    This paper provides an analysis of a log detector in order to determine its response to a multitone input for detection of spurious emissions in a radio frequency transmitter. Treatment is given to the single tone response of the log detector and extended to a two-tone log detector system, where a large signal and a small signal are present. The large signal is observed to experience logarithmic processing with an output at zero frequency. The small signal produces an output at the difference frequency of the large signal frequency and small signal frequency that is approximately proportional to the ratio of the small signal voltage to the large signal voltage. The two-tone results are generalized to an m-tone input. Experimental results are presented to show the accuracy of the model. The log detector circuit analyzed is able to detect a spurious emission within 45 MHz of the main signal with plusmn1 dB of accuracy. View full abstract»

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  • A Low-Power Multicarrier-CDMA Downlink Baseband Receiver for Future Cellular Communication Systems

    Publication Year: 2007 , Page(s): 2229 - 2239
    Cited by:  Papers (7)
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (2625 KB) |  | HTML iconHTML  

    In this paper, design and implementation of a baseband receiver integrated circuit (IC) for a downlink multi-carrier code-division multiple access (MC-CDMA) system are presented. This MC-CDMA system aims to provide higher data transmission capacity than the current wide-band CDMA systems in mobile cellular communication environments. The proposed chip provides a robust tracking mechanism for synchronization errors and an accurate channel estimation strategy to overcome the challenge of outdoor fast-fading channels. Besides, low-power and low-complexity architecture design techniques are adopted to satisfy mobile receiver needs. Experimental results of the designed baseband receiver integrated circuit demonstrate its superior system performance and great reduction in power consumption. The chip was fabricated in a 0.18-mum CMOS technology with a core area of 2.6 mm times 2.6 mm. It can support up to 21.7-Mbps uncoded data rate in a 5-MHz bandwidth. When running at 5.76 MHz, its power consumption is as low as 9.9 mW from a supply voltage of 1.1 V. View full abstract»

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  • A Versatile Variable Rate LDPC Codec Architecture

    Publication Year: 2007 , Page(s): 2240 - 2251
    Cited by:  Papers (12)  |  Patents (3)
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (680 KB) |  | HTML iconHTML  

    This paper presents a system architecture for low-density parity-check (LDPC) codes that allows dynamic switching of LDPC codes within the encoder and decoder without hardware modification of these modules. Thus, rate compatibility is facilitated without the performance degradation inherent in a puncture-based system. This versatility also allows the LDPC system to be used in a variety of applications since the encoder and decoder can be used with codes that span a wide range of lengths and rates. View full abstract»

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  • Theoretical Upperbound of the Spurious-Free Dynamic Range in Direct Digital Frequency Synthesizers Realized by Polynomial Interpolation Methods

    Publication Year: 2007 , Page(s): 2252 - 2261
    Cited by:  Papers (13)
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (571 KB) |  | HTML iconHTML  

    In this paper, a universal mathematical method is proposed to determine the upperbound of the spurious-free dynamic range (SFDR) in direct digital frequency synthesizers (DDFSs) realized by piecewise polynomial interpolation methods. The Fourier series is used to establish a linear matrix relationship between the frequency spectrum of the interpolated sinusoidal signal and the coefficients of the interpolating polynomials. This matrix relationship can be considered as a linear overdetermined system of equations, which can be solved for the ideal spectrum where the fundamental harmonic has an amplitude of one and the other harmonics are zero. It is shown that the Moore-Penrose pseudoinverse and Chebyshev minimax methods find the coefficients corresponding to the largest signal-to-noise ratio and maximum SFDR designs, respectively. The proposed method is used to show that the maximum SFDR of a DDFS based on the even fourth-order polynomial interpolation is 74.35 dBc. A DDFS based on the aforementioned method is designed and its architecture is optimized to obtain an SFDR of 72.2 dBc. A VLSI implementation of the proposed DDFS is also reported. View full abstract»

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  • Synthesis of Narrowband Linear-Phase FIR Filters With a Piecewise-Polynomial Impulse Response

    Publication Year: 2007 , Page(s): 2262 - 2276
    Cited by:  Papers (9)
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (843 KB) |  | HTML iconHTML  

    Classes of linear-phase finite-impulse response (FIR) filters with a piecewise-polynomial impulse response are proposed for the four types of linear-phase FIR filters. In addition, very efficient recursive structures to implement these filters in a straightforward and consistent manner are proposed. The desired impulse response is created by using a parallel connection of several filter branches. Only one branch has an impulse response of the full filter length, whereas the impulse responses are shorter for the remaining branches but the center is at the same location. The arithmetic complexity of these filters is proportional to the number of branches and the common polynomial order for each branch, rather than the actual filter order. In order to generate the overall piecewise-polynomial impulse response the polynomial coefficients are found, with the aid of linear programming, by optimizing the responses in the minimax sense, for both narrowband conventional filters and narrowband differentiators. The generation of these structures is based on the use of accumulators so that after using an accumulator, the resulting impulse response is divided into two parts. The first part follows the desired polynomial form, and the second part is what is left after the division, i.e., the nonpolynomial part. This same procedure can be used for all the following accumulators. Several examples are included, illustrating the benefits of the proposed filters, in terms of a reduced number of unknowns used in the optimization and the reduced number of multipliers required in the actual implementation. View full abstract»

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  • CNN-Based Hybrid-Order Texture Segregation as Early Vision Processing and Its Implementation on CNN-UM

    Publication Year: 2007 , Page(s): 2277 - 2287
    Cited by:  Papers (5)
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (4137 KB) |  | HTML iconHTML  

    In this paper, a biologically inspired, CNN-based, multi-channel, texture boundary detection technique is presented. The proposed approach is similar to human vision system. The algorithm is simple and straightforward such that it can be implemented on the cellular neural networks (CNNs). CNN contains several important advantages, such as efficient real-time processing capability and feasible very large-scale integration (VLSI) implementation. The proposed algorithm also had been widely tested on synthetic texture images. Those texture images are randomly selected from the Brodatz textures database (1966). According to our simulation results, the boundaries of uniform textures can be detected quite successfully. For the nonuniform or nonregular textures, the results also indicate meaningful properties, and the properties also are consistent to the human visual sensation. The proposed algorithm also has been implemented on the CNN universal machine (CNN-UM), and yields similar results as the simulation on the PC. Based on the efficient performance of CNN-UM, the algorithm becomes very fast. View full abstract»

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  • Stability Criteria for Impulsive Systems With Time Delay and Unstable System Matrices

    Publication Year: 2007 , Page(s): 2288 - 2298
    Cited by:  Papers (19)
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (537 KB) |  | HTML iconHTML  

    This paper studies stability problems of a class of impulsive systems with time delay whose linear parts contain unstable system matrices. By using the method of variation of parameters, Lyapunov functions and inequalities, several stability criteria are established for both linear and nonlinear impulsive systems with time delay. It is shown that the time delay systems can be stabilized by impulses even if the system matrices are unstable. Several numerical examples are given to illustrate the results. View full abstract»

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  • Chip Pulse Shaping in Asynchronous Chaos-Based DS-CDMA

    Publication Year: 2007 , Page(s): 2299 - 2314
    Cited by:  Papers (7)
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (768 KB) |  | HTML iconHTML  

    This paper extends and fully formalizes some previous results by developing an analytical method to account for the general chip pulse for DS-CDMA systems in an asynchronous environment with an integrate-and-dump receiver, applying it to commonly used pulses. Given the pulse, such a formal method allows us to define the optimum spreading code autocorrelation to be used and the relative signal-to-interference ratio performance. A chaos-based spreading code is plugged into this model to show that such an optimum performance can be very well approximated by practical sequence generators. This is shown by analyzing some typical bandlimited and substantially bandlimited pulses and determining the optimum spreading for each of them. These results prove that the gain of chaos-based spreading over conventional i.i.d.-like spreading can reach 75% when practical bandlimited pulses are considered. View full abstract»

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  • Passive Multiterminal Networks Without Transformers

    Publication Year: 2007 , Page(s): 2315 - 2320
    Cited by:  Papers (2)
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (210 KB) |  | HTML iconHTML  

    It is known that any scalar function f(p) of the complex frequency variable that is the admittance function of a passive finite network is in fact the admittance function of a network that can be realized without transformers. This paper shows that an m times m matrix-valued function Y(p), m ges 2, given that it is an admittance matrix, is the admittance of a network that contains no transformers if and only if it enjoys two further properties: 1) for each real p > 0 Y(p) is the admittance of a passive resistive network specific to p; and 2) a property defined as the null space property. It is shown that property 1) severely limits the class of m-terminal networks, m > 1, that can be realized without transformers. The author concludes that, for passive systems, transformers are here to stay. View full abstract»

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  • Analytical Equations for Nonlinear Phase Errors and Jitter in Ring Oscillators

    Publication Year: 2007 , Page(s): 2321 - 2329
    Cited by:  Papers (16)
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (484 KB) |  | HTML iconHTML  

    In this paper, we present a simple analytical equation for capturing phase errors in 3-stage ring oscillators. The model, based on a simple but useful idealization of the ring oscillator, is provably exact for small noise perturbations. Despite its simplicity and purely analytical form, our model correctly captures the time- dependent sensitivity of oscillator phase to external perturbations. It is thus well suited for estimating both qualitative and quantitative features of ring oscillator phase response to internal noises, as well as to power, ground and substrate interference. The nonlinear nature of the model makes it suitable for predicting injection locking as well. Comparisons of the new model with existing phase models are provided, and its application for correct prediction of thermal jitter demonstrated. Requiring knowledge only of the amplitude and frequency of the oscillator, the model is ideally suited for early design exploration at the system and circuit levels. View full abstract»

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  • Design of Linear Phase FIR Filters in Subexpression Space Using Mixed Integer Linear Programming

    Publication Year: 2007 , Page(s): 2330 - 2338
    Cited by:  Papers (34)
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (497 KB) |  | HTML iconHTML  

    In this paper, a novel optimization technique is proposed to optimize filter coefficients of linear phase finite-impulse response (FIR) filter to share common subexpressions within and among coefficients. Existing approaches of common subexpression elimination optimize digital filters in two stages: first, an FIR filter is designed in a discrete space such as finite wordlength space or signed power-of-two (SPT) space to meet a given specification; in the second stage, an optimization algorithm is applied on the discrete coefficients to find and eliminate the common subexpressions. Such a two-stage optimization technique suffers from the problem that the search space in the second stage is limited by the finite wordlength or SPT coefficients obtained in the first stage optimization. The new proposed algorithm overcomes this problem by optimizing the filter coefficients directly in subexpression space for a given specification. Numerical examples of benchmark filters show that the required number of adders obtained using the proposed algorithm is much less than those obtained using two-stage optimization approaches. View full abstract»

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  • 2008 IEEE International Symposium on Circuits and Systems-engineering the environmental revolution (ISCAS 2008)

    Publication Year: 2007 , Page(s): 2339
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    Freely Available from IEEE

Aims & Scope

The theory, analysis, design, and practical implementations of circuits, and the application of circuit techniques to systems and to signal processing.

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Editor-in-Chief
Shanthi Pavan
Indian Institute of Technology, Madras