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IEEE Design & Test of Computers

Issue 5 • Sept.-Oct. 2007

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Displaying Results 1 - 25 of 29
  • [Front cover]

    Publication Year: 2007, Page(s): c1
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  • IEEE Computer Society Digital Library

    Publication Year: 2007, Page(s): c2
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  • Call for Papers: Special Issue on Design and Test of Interconnects for Multicore Chips

    Publication Year: 2007, Page(s): 409
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  • Table of contents

    Publication Year: 2007, Page(s):410 - 411
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  • Combining synchronous and asynchronous timing schemes for high-performance systems

    Publication Year: 2007, Page(s): 412
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  • [Masthead]

    Publication Year: 2007, Page(s): 413
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  • Guest Editors' Introduction: GALS Design and Validation

    Publication Year: 2007, Page(s):414 - 416
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (130 KB) | HTML iconHTML

    Globally asynchronous, locally synchronous (GALS) design has grown in popularity in both academia and industry. Breaking the synchrony assumption in digital design is often unsettling for designers, and to alleviate the difficulty, researchers in EDA have been proposing various GALS-based solutions. However, the tools, verification techniques, and testing methodologies for asynchronous designs are... View full abstract»

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  • Advertiser/Product Index

    Publication Year: 2007, Page(s): 417
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  • A Survey and Taxonomy of GALS Design Styles

    Publication Year: 2007, Page(s):418 - 428
    Cited by:  Papers (81)  |  Patents (1)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (691 KB) | HTML iconHTML

    Single-clocked digital systems are largely a thing of the past. Although most digital circuits remain synchronous, many designs feature multiple clock domains, often running at different frequencies. Using an asynchronous interconnect decouples the timing issues for the separate blocks. Systems employing such schemes are called globally asynchronous, locally synchronous (GALS). To minimize time to... View full abstract»

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  • Computing in Science and Engineering 2007 Editorial Calendar

    Publication Year: 2007, Page(s): 429
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  • Globally Asynchronous, Locally Synchronous Circuits: Overview and Outlook

    Publication Year: 2007, Page(s):430 - 441
    Cited by:  Papers (99)  |  Patents (2)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (1110 KB) | HTML iconHTML

    This article provides a pragmatic survey on the state of the art in GALS architectural techniques, design flows, and applications. The authors also prescribe several industrial inventions and changes in methodology, tools, and design flow that would improve GALS-based integration of IP blocks. View full abstract»

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  • Adaptive Latency-Insensitive Protocols

    Publication Year: 2007, Page(s):442 - 452
    Cited by:  Papers (14)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (1003 KB) | HTML iconHTML

    Latency-insensitive protocols (LIPs) represent a class of interblock protocols designed to overcome long multiclock interconnects. This article presents an adaptive solution to this problem, which the authors show to be more effective than earlier solutions in terms of power, area, and throughput. View full abstract»

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  • IEEE Software 2007 Editorial Calendar

    Publication Year: 2007, Page(s): 453
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  • A GALS Infrastructure for a Massively Parallel Multiprocessor

    Publication Year: 2007, Page(s):454 - 463
    Cited by:  Papers (76)  |  Patents (5)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (850 KB) | HTML iconHTML

    This case study focuses on a massively parallel multiprocessor for real-time simulation of billions of neurons. Every node of the design comprises 20 ARM9 cores, a memory interface, a multicast router, and two NoC structures for communicating between internal cores and the environment. The NoCs are asynchronous; the cores and RAM interfaces are synchronous. This GALS approach decouples clocking co... View full abstract»

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  • A Highly Scalable GALS Crossbar Using Token Ring Arbitration

    Publication Year: 2007, Page(s):464 - 472
    Cited by:  Papers (2)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (1432 KB) | HTML iconHTML

    With increases in die size and clock frequency, driving signals across dies is becoming increasingly more difficult. To reduce clock skew and power, the general trend is to use multiple clock domains on a single die, making both synchronous and asynchronous interclock domain communication possible. The 2005 International Technology Roadmap for Semiconductors states that asynchronous global signali... View full abstract»

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  • IEEE Pervasive Computing Subscription

    Publication Year: 2007, Page(s): 473
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  • Guest Editor's Introduction: Getting More Out of Test

    Publication Year: 2007, Page(s):474 - 475
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  • X-Tolerant Compactor with On-Chip Registration and Signature-Based Diagnosis

    Publication Year: 2007, Page(s):476 - 485
    Cited by:  Papers (1)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (706 KB) | HTML iconHTML

    This article describes a two-stage test response compactor with an overdrive section, scan chain selection logic, and an on-chip comparator and registration scheme for efficient signature-based diagnosis. This solution offers compaction ratios much higher than those determined by the ratio of scan chains to compactor outputs, and it guarantees very good observability and diagnostic resolution of s... View full abstract»

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  • Cell Broadband Engine Debugging for Unknown Events

    Publication Year: 2007, Page(s):486 - 493
    Cited by:  Papers (10)  |  Patents (69)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (571 KB) | HTML iconHTML

    The complexity of today's hundreds-of-million-transistor microprocessors all but guarantees imperfect first silicon, but leaves unanswered the question of what exactly will go wrong. This article describes features added to the cell broadband engine processor to enable debugging in the presence of such unknown events. View full abstract»

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  • The Psychology of Electronic Test

    Publication Year: 2007, Page(s):494 - 501
    Cited by:  Papers (4)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (571 KB) | HTML iconHTML

    Test-related decisions have important consequences for product cost, quality, reliability, and information gathering. Yet, the persons making those decisions are - like all of us - imperfect. This article suggests ways to improve our understanding of our own decision making with an eye toward making the best choices possible in the area of electronic test. View full abstract»

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  • DAC Highlights

    Publication Year: 2007, Page(s):502 - 504
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  • DATC Newsletter

    Publication Year: 2007, Page(s): 505
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  • Book Reviews: Test Tutorials in Book Form

    Publication Year: 2007, Page(s):506 - 507
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  • CEDA Currents

    Publication Year: 2007, Page(s):508 - 509
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  • DATE 07 workshop on diagnostic services in NoCs

    Publication Year: 2007, Page(s): 510
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Aims & Scope

This Periodical ceased production in 2012. The current retitled publication is IEEE Design & Test.

Full Aims & Scope

Meet Our Editors

Editor-in-Chief
Krishnendu Chakrabarty