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IEEE Transactions on Computers

Issue 11 • Nov. 2007

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Displaying Results 1 - 16 of 16
  • [Front cover]

    Publication Year: 2007, Page(s): c1
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    Freely Available from IEEE
  • [Inside front cover]

    Publication Year: 2007, Page(s): c2
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  • Near-Memory Caching for Improved Energy Consumption

    Publication Year: 2007, Page(s):1441 - 1455
    Cited by:  Papers (5)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (3440 KB) | HTML iconHTML

    The main memory has become one of the largest contributors to overall energy consumption and offers many opportunities for power/energy reduction. In this paper, we propose a power-aware cached-dynamic-RAM (PA-CDRAM) organization that integrates a moderately sized cache directly into a memory chip. We use this near-memory cache to turn a memory bank off immediately after it is accessed to reduce p... View full abstract»

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  • On the Access Pricing and Network Scaling Issues of Wireless Mesh Networks

    Publication Year: 2007, Page(s):1456 - 1469
    Cited by:  Papers (32)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (1786 KB) | HTML iconHTML

    Distributed wireless mesh network technology is ready for public deployment in the near future. However, without an incentive system, one should not assume that private self-interested wireless nodes would participate in such a public network and cooperate in the packet forwarding service. This paper studies the use of pricing as an incentive mechanism for stimulating participation and collaborati... View full abstract»

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  • A Novel Architecture for Galois Fields GF(2^m) Multipliers Based on Mastrovito Scheme

    Publication Year: 2007, Page(s):1470 - 1483
    Cited by:  Papers (12)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (4826 KB) | HTML iconHTML

    In this paper, a new GF(2m) multiplier for standard-basis representation is developed. The proposed multiplier implements the Mastrovito multiplication scheme and can be designed for every field GF(2m). A minimum-area implementation of the first block of Mastrovito multiplier and a high-speed delay-driven tree architecture for the second block of the Mastrovito multiplier are... View full abstract»

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  • Fast Parallel-Prefix Architectures for Modulo 2n-1 Addition with a Single Representation of Zero

    Publication Year: 2007, Page(s):1484 - 1492
    Cited by:  Papers (30)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (1976 KB) | HTML iconHTML

    Novel modulo 2n-1 addition algorithms for residue number system (RNS) applications are presented. The proposed algorithms depart from the traditional approach of modulo 2n-1 addition by setting the input carry in the first stage of the addition to one, which only ever produces one representation of zero. The resulting architectures not only offer significant speedup in a modu... View full abstract»

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  • On Periodic Register Need in Software Pipelining

    Publication Year: 2007, Page(s):1493 - 1504
    Cited by:  Papers (3)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (1355 KB) | HTML iconHTML

    This paper presents several theoretical and fundamental results on the register need in periodic schedules, also known as MAXLIVE. Our first contribution is a novel formula for computing the exact number of registers needed by a scheduled loop. This formula has two advantages: Its computation can be done by using a polynomial algorithm with O(n lg n) complexity (n is the number of instructions in ... View full abstract»

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  • A Verifiable Language for Programming Real-Time Communication Schedules

    Publication Year: 2007, Page(s):1505 - 1519
    Cited by:  Papers (17)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (1420 KB) | HTML iconHTML

    Distributed hard real-time systems require predictable communication at the network level and verifiable communication behavior at the application level. At the network level, communication between nodes must be guaranteed to happen within bounded time and one common approach is to restrict the network access by enforcing a time-division multiple access (TDMA) schedule. At the application level, t... View full abstract»

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  • Applying Statistical Sampling for Fast and Efficient Simulation of Commercial Workloads

    Publication Year: 2007, Page(s):1520 - 1533
    Cited by:  Papers (1)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (3266 KB) | HTML iconHTML

    Commercial workloads form an important class of applications and have performance characteristics that are distinct from scientific and technical benchmarks such as the SPEC CPU. However, due to the prohibitive simulation time of commercial workloads, it is extremely difficult to use them in computer architecture research. In this paper, we study the efficacy of using statistical sampling-based si... View full abstract»

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  • Scalable Dynamic Instruction Scheduler through Wake-Up Spatial Locality

    Publication Year: 2007, Page(s):1534 - 1548
    Cited by:  Papers (2)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (5219 KB) | HTML iconHTML

    In a high-performance superscalar processor, the instruction scheduler often comes with poor scalability and high complexity due to the expensive wake-up operation. From detailed simulation-based analyses, we find that 95 percent of the wake-up distances between two dependent instructions are short, in the range of 16 instructions, and 99 percent are in the range of 31 instructions. We apply this ... View full abstract»

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  • Speed versus Accuracy Trade-Offs in Microarchitectural Simulations

    Publication Year: 2007, Page(s):1549 - 1563
    Cited by:  Papers (4)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (5766 KB) | HTML iconHTML

    Due to the long simulation time of the reference input set, computer architects often use reduced time simulation techniques to shorten the simulation time. However, what has not yet been thoroughly evaluated is the accuracy of these techniques relative to the reference input set and with respect to each other. To rectify this deficiency, this paper uses three methods to characterize reduced input... View full abstract»

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  • Efficient Algorithms for the Inverse Sort Transform

    Publication Year: 2007, Page(s):1564 - 1574
    Cited by:  Papers (5)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (1889 KB) | HTML iconHTML

    As an important variant of the Burrows-Wheeler Transform (BWT), the Sort Transform (ST) can speed up the transformation by sorting only a portion of the matrix. However, because the currently known inverse ST algorithms need to retrieve the complete k-order contexts and use hash tables, they are less efficient than the inverse BWT. In this paper, we propose three fast and memory-efficient inverse ... View full abstract»

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  • On the Hardness of Approximating the Multicast Delay Variation Problem

    Publication Year: 2007, Page(s):1575 - 1577
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (200 KB) | HTML iconHTML

    Given a network with one source and multiple destinations, the multicast delay variation problem attempts to construct a multicast tree such that the interdestination delay variation among all the paths from the source to each destination is minimized. In this paper, we show that the problem is NP-hard and that it is not approximable within a constant factor in polynomial time unless NP = P. These... View full abstract»

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  • Temporal Predicate Detection Using Synchronized Clocks

    Publication Year: 2007, Page(s):1578 - 1584
    Cited by:  Papers (9)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (1692 KB) | HTML iconHTML

    Advances in clock synchronization techniques allow an approximated global time in ubiquitous environments. This paper presents an event stream- based online algorithm that fuses the data reported from the processors in such a network to detect time-based predicates. The algorithm has low space, time, and message complexities. The paper also considers the detection of simultaneous events as a speci... View full abstract»

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  • TC Information for authors

    Publication Year: 2007, Page(s): c3
    Request permission for commercial reuse | PDF file iconPDF (82 KB)
    Freely Available from IEEE
  • [Back cover]

    Publication Year: 2007, Page(s): c4
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    Freely Available from IEEE

Aims & Scope

The IEEE Transactions on Computers is a monthly publication with a wide distribution to researchers, developers, technical managers, and educators in the computer field.

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Meet Our Editors

Editor-in-Chief
Paolo Montuschi
Politecnico di Torino
Dipartimento di Automatica e Informatica
Corso Duca degli Abruzzi 24 
10129 Torino - Italy
e-mail: pmo@computer.org