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Circuits and Systems II: Express Briefs, IEEE Transactions on

Issue 9 • Date Sept. 2007

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Displaying Results 1 - 23 of 23
  • Table of contents

    Page(s): C1 - C4
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    Freely Available from IEEE
  • IEEE Transactions on Circuits and Systems—II: Express Briefs publication information

    Page(s): C2
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  • CMOS High-CMRR Current Output Stages

    Page(s): 745 - 749
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (695 KB) |  | HTML iconHTML  

    Two CMOS current output stages are presented. Compared to the traditional solution, which exhibits unbalanced operation, the proposed ones exploit an auxiliary high-gain feedback loop which provides differential drive, thereby highly improving the common-mode rejection ratio (CMRR). Prototypes are designed and fabricated in a 0.35-mum technology and experimental results confirm that a CMRR increase greater than 20 dB can be achieved and, for one of the two solutions, without increasing the voltage requirements. View full abstract»

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  • A Wide Locking-Range Frequency Divider for LMDS Applications

    Page(s): 750 - 754
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (1718 KB) |  | HTML iconHTML  

    A fully integrated frequency divider with an operation frequency up to 20 GHz is designed in 0.18-mum CMOS technology. The frequency divider includes two stages to divide the input signal by a factor of 4. A wide locking range from 18.8 to 23.2 GHz was obtained with a low phase noise of -134.8 dBc/Hz (1-MHz offset) at an output frequency of 4.7 GHz. The first stage is designed by an analog methodology with the varactors to extend the locking range, while the second stage is designed by a digital approach with the RF devices for a high operation frequency. With the advantages of both designs, this frequency divider is operated at the frequency range suitable for LMDS applications. View full abstract»

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  • A High Slew-Rate Push–Pull Output Amplifier for Low-Quiescent Current Low-Dropout Regulators With Transient-Response Improvement

    Page(s): 755 - 759
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (439 KB) |  | HTML iconHTML  

    A high slew-rate amplifier with push-pull output driving capability is proposed to enable an ultra-low quiescent current (Iq ~ 1muA) low-dropout (LDO) regulator with improved transient responses. The proposed amplifier eliminates the tradeoff between small Iq and large slew-rate that is imposed by the tail-current in conventional amplifier design. Push-pull output stage is introduced to enhance the output driving ability. Small dropout voltage (Vbo) with large-size pass transistor and ultra-low Iq can thus be used to minimize power loss of LDO regulator without transient-response degradation. The proposed amplifier helps to improve stability of LDO regulators without using any on-chip and off-chip compensation capacitors. This is beneficial to chip-level power management requiring high-area efficiency. An LDO regulator with the proposed amplifier has been implemented in a 0.18- mum standard CMOS process and occupies 0.09 mm2. The LDO regulator can deliver 50-mA load current at 1-V input and ~ 100-mV VDO . It only consumes 1.2 muA Iq and is able to recover within ~ 4 mus even under the worst case scenario. View full abstract»

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  • The Stochastic I-Pot: A Circuit Block for Programming Bias Currents

    Page(s): 760 - 764
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (740 KB) |  | HTML iconHTML  

    In this brief, we present the "stochastic I-Pot." It is a circuit element that allows for digitally programming a precise bias current ranging over many decades, from pico-amperes up to hundreds of micro-amperes. I-Pot blocks can be chained within a chip to allow for any arbitrary number of programmable bias currents. The approach only requires to provide the chip with three external pins, the use of an external current measuring instrument, and a computer. This way, once all internal I-Pots have been characterized, they can be programmed through a computer to provide any desired current bias value with very low error. The circuit block turns out to be very practical for experimenting with new circuits (specially when a large number of biases are required), testing wide ranges of biases, introducing means for current mismatch calibration, offsets compensations, etc. using a reduced number of chip pins. We show experimental results of generating bias currents with errors of 0.38% (8 bits) for currents varying from 176 muA to 19.6 pA. Temperature effects are characterized. View full abstract»

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  • An ARM-Based System-on-a-Programmable-Chip Architecture for Spoken Language Translation

    Page(s): 765 - 769
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (1193 KB)  

    Previous research shows that there are two architectures for spoken language translation (SLT) system implementation. One is client-server based systems that should be built on the server computer but unreliability of the remote connection. The other is to build portable stand-alone devices but it lacks realtime performance. In this brief, a system-on-a-programmable-chip (SoPC) solution is proposed by realizing the entire SLT system within a single chip. This SoPC is characterized by small size, low cost, real-time operation, and high portability. This entire design was implemented on ALTERA EPXA10 device. Performance for English-to-Mandarin translation process can be completed within 1 s at a 46.22-MHz clock frequency with 3000 translation patterns. The total logic usage of the EPXA10 device is 50% (about 19318 logic cells). View full abstract»

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  • Multiplierless, Folded 9/7– 5/3 Wavelet VLSI Architecture

    Page(s): 770 - 774
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (294 KB) |  | HTML iconHTML  

    This brief proposes a multiplierless VLSI architecture for the famous 9/7 wavelet filters. The novelty of this architecture is the possibility to compute the 5/3 wavelet results into the 9/7 data path with a reduced number of adders compared to other solutions. The multiplierless architecture has been characterized in terms of performance through simulations into a JPEG2000 environment and compared to other solutions. Implementation on a 0.13-mum standard cell technology shows that the proposed architecture compared to other multiplierless architectures requires a reduced amount of logic with excellent performance. View full abstract»

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  • RNS-To-Binary Converter for a New Three-Moduli Set {2n+1−1,2n,2n−1}

    Page(s): 775 - 779
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (270 KB) |  | HTML iconHTML  

    In this brief, the design of residue number system (RNS) to binary converters for a new powers-of-two related three-moduli set {2n+1 - 1, 2n, 2n - 1} is considered. This moduli set uses moduli of uniform word length (n to n + 1 bits). It is derived from a previously investigated four-moduli set {2n - 1, 2n, 2n + 1, 2n +1 - 1}. Three RNS-to-binary converters are proposed for this moduli set: one using mixed radix conversion and the other two using Chinese remainder theorem. Detailed architectures of the three converters as well as comparison with some earlier proposed converters for three-moduli sets with uniform word length and the four-moduli set {2n - 1, 2n, 2n + 1, 2n+1 - 1} are presented. View full abstract»

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  • Optimal Use of Some Classical Approximations in Filter Design

    Page(s): 780 - 784
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (333 KB) |  | HTML iconHTML  

    The classical Butter worth, Chebyshev and Elliptic (Cauer) low-pass filter approximations can be used in the design of analog and IIR digital filters in such a way as to obtain passband, stopband and transition band optimized filters at no order cost. The exact analytical relationships for such an optimal deployment of these approximations are developed and presented in this paper and their use is demonstrated through design examples. View full abstract»

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  • A Complex Variable Fractional-Delay FIR Filter Structure

    Page(s): 785 - 789
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (240 KB) |  | HTML iconHTML  

    This brief introduces a structure for complex variable fractional delay (FD) finite-length impulse response (FIR) filters. The structure is derived from a real variable FD FIR filter and is constituted by a set of fixed real linear-phase FIR filters and two multiply-accumulate chains containing variable multipliers. In this way the implementation complexity and delay may be reduced in comparison with the cascade approach which hitherto has been used for the same purpose. A design example is included to demonstrate the benefits of the new structure. View full abstract»

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  • Polyphase Conditions and Structures for 2-D Quincunx FIR Filter Banks Having Quadrantal or Diagonal Symmetries

    Page(s): 790 - 794
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (362 KB) |  | HTML iconHTML  

    In this brief, we derive conditions on the polyphase matrix of 2-D finite-impulse response (FIR) quincunx filter banks, for the filters in the filter bank to have quadrantal or diagonal symmetry. These conditions provide a framework for synthesizing polyphase structures which structurally enforce the symmetry. This is demonstrated by constructing examples of small parameterized matrix structures which satisfy the above conditions, thus giving perfect reconstruction FIR quincunx filter banks with quadrantal or diagonally symmetric short-kernel (i.e., short-support) filters. It is also shown that cascades of the above constructed small structures can be used to construct filters of higher order. View full abstract»

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  • More on Security of Public-Key Cryptosystems Based on Chebyshev Polynomials

    Page(s): 795 - 799
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (138 KB) |  | HTML iconHTML  

    Recently, a public-key cryptosystem based on Chebyshev polynomials has been proposed, but it has been later analyzed and shown insecure. This paper addresses some unanswered questions about the cryptosystem. We deal with the issue of computational precision. This is important for two reasons. Firstly, the cryptosystem is defined on real numbers, but any practical data communication channel can only transmit a limited number of digits. Any real number can only be specified to some precision level, and we study the effect of that. Secondly, we show that the precision issue is related to its security. In particular, the algorithm previously proposed to break the cryptosystem may not work in some situations. Moreover, we introduce another method to break the cryptosystem with general precision settings. We extend the method to show that a certain class of cryptosystems is insecure. Our method is based on the known techniques on the shortest vector problem in lattice and linear congruences. View full abstract»

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  • Remarks on Analysis, Design and Amplitude Stability of MOS Colpitts Oscillator

    Page(s): 800 - 804
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (329 KB) |  | HTML iconHTML  

    The small-signal analysis shows that the MOS Colpitts oscillator is described by a third order characteristic equation. The procedure for finding the second order approximation is defined, and the solution corresponding to this approximation is found. Then the equations for transistor transconductance describing function are analyzed, and the design procedure corresponding to the "convenient" operation point is given. The same equations are also used for the analysis of amplitude stability in this oscillator. It is shown that the amplitude self-modulation (squegging) in the considered oscillator is absent for any conducting angle of the transistor. View full abstract»

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  • Control of Fast Scale Bifurcations in Power-Factor Correction Converters

    Page(s): 805 - 809
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (263 KB) |  | HTML iconHTML  

    This brief proposes a novel controller which greatly enhances the performance of a power-factor correction converter. This controller is optimally tuned to place the eigenvalues of the system well inside the unit circle and hence it guarantees stable operation over a wide range of input voltages. The design of the controller is based on the stability analysis of the system using the state transition matrix over a clock cycle. It is shown that the transition matrix across the switching manifold greatly influences the system's performance, allowing the system to be stabilized by periodically altering the manifold. The results are validated by analytical and numerical studies. View full abstract»

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  • Active Q-Factor and Equilibrium Stability Formulation for Sinusoidal Oscillators

    Page(s): 810 - 814
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (167 KB) |  | HTML iconHTML  

    Quality factor (Q-factor) and stability criterion of sinusoidal oscillators are formulated from the viewpoints of energy equilibrium and spectrum purity. Complex power works as an objective function to determine the steady-state oscillation amplitude and frequency. Conjugate product of amplitude and frequency slopes of the function dominates equilibrium stability. Logarithmic derivative of oscillator's output impedance defines active Q-factor, which takes into account effects of positive power generated by active devices, while keeping its non-divergent property. Transfer Q -factor is also defined for oscillating networks involving noise sources on different branches from the port of spectrum observation. Presented formulas can be applied to the entire oscillator circuit without de-embedding active devices, and thus they enable frequency-domain CAD simulators to numerically evaluate oscillator performance. View full abstract»

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  • IP Observer Design for Descriptor Linear Systems

    Page(s): 815 - 819
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    The new type of integral proportional (IP) observers for descriptor linear systems is proposed. Based on a parametric solution to a type of matrix equations, a parametric approach for the design of the IP observers is established. The proposed approach guarantees the regularity of the observer systems, and gives parameterizations of all observer gains in terms of some free parameters. View full abstract»

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  • A Subsampling Quadrature Σ∆ Modulator Based on Distributed Resonators for Use in Radio Receiver

    Page(s): 820 - 824
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (481 KB) |  | HTML iconHTML  

    The receiver architecture proposed in this brief seizes the subsampling properties of continuous-time sigma-delta (SigmaDelta) modulators based on distributed resonators to construct a quadrature receiver. The proposed architecture is based on a low-pass SigmaDelta modulator that subsamples an intermediate frequency signal around the sampling frequency and does not require quadrature mixers. Instead, the quadrature mixing is replaced by suitably choosing the sampling instants inside the loop. Two practical circuit implementations are proposed. The first one uses separate circuitry for the I and Q paths. The second architecture introduces an innovative way to produce the I and Q outputs that is immune to path mismatch due to the sharing of all the analog circuitry for both paths. The proposed modulator may be feasible for the typical IF frequencies used in cellular base stations. View full abstract»

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  • Fast-Transient PCCM Switching Converter With Freewheel Switching Control

    Page(s): 825 - 829
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (1018 KB) |  | HTML iconHTML  

    This brief presents a new switching converter operating in pseudo-continuous-conduction mode (PCCM) with freewheel switching control. Compared with conventional discontinuous-conduction mode (DCM) converters, this converter demonstrates much improved current handling capability with reduced current and voltage ripples. The control-to-output transfer function exhibits a single-pole behavior, making the load transient response much faster than its CCM counterparts. Simulation and experimental results show that, with a 6-V, 6-W load and a 10-V unregulated supply, the PCCM converter has a current ripple of only 1.1 A and a ripple voltage of only 58 mV, while a DCM converter has a current ripple of 2.2 A and a ripple voltage of 220 mV. In addition, the PCCM converter takes only 25 mus to respond to a 500-mA load current change while a CCM one requires 1.4 ms. View full abstract»

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  • Special issue on multifunctional circuits and systems for future generations of wireless communications

    Page(s): 830
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  • 2008 IEEE International Symposium on Circuits and Systems-engineering the environmental revolution (ISCAS 2008)

    Page(s): 831
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    Freely Available from IEEE
  • IEEE Transactions on Circuits and Systems—II: Express Briefs Information for authors

    Page(s): 832
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  • IEEE Circuits and Systems Society Information

    Page(s): C3
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Aims & Scope

TCAS II publishes brief papers in the field specified by the theory, analysis, design, and practical implementations of circuits, and the application of circuit techniques to systems and to signal processing. Included is the whole spectrum from basic scientific theory to industrial applications. The field of interest covered includes:

  • Circuits: Analog, Digital and Mixed Signal Circuits and Systems  
  • Nonlinear Circuits and Systems, Integrated Sensors, MEMS and Systems on Chip, Nanoscale Circuits and Systems, Optoelectronic
  • Circuits and Systems, Power Electronics and Systems
  • Software for Analog-and-Logic Circuits and Systems
  • Control aspects of Circuits and Systems. 

Full Aims & Scope