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Circuits and Systems I: Regular Papers, IEEE Transactions on

Issue 9 • Date Sept. 2007

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Displaying Results 1 - 25 of 29
  • Table of contents

    Publication Year: 2007 , Page(s): C1 - C4
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    Freely Available from IEEE
  • IEEE Transactions on Circuits and Systems—I: Regular Papers publication information

    Publication Year: 2007 , Page(s): C2
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  • Pulsewidth Modulation Circuits Using CMOS OTAs

    Publication Year: 2007 , Page(s): 1869 - 1878
    Cited by:  Papers (10)  |  Patents (1)
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (583 KB) |  | HTML iconHTML  

    This paper presents three pulsewidth modulation modulators using CMOS operational transconductance amplifiers. They consist of a ramp integrator and current-tunable Schmitt triggers. Prototype circuits built using discrete components exhibited that their duty cycles are linearly controllable. Because of their simple structure, the proposed modulators can be easily fabricated in a monolithic integrated circuit. View full abstract»

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  • Full On-Chip CMOS Low-Dropout Voltage Regulator

    Publication Year: 2007 , Page(s): 1879 - 1890
    Cited by:  Papers (133)  |  Patents (7)
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (1617 KB) |  | HTML iconHTML  

    This paper proposes a solution to the present bulky external capacitor low-dropout (LDO) voltage regulators with an external capacitorless LDO architecture. The large external capacitor used in typical LDOs is removed allowing for greater power system integration for system-on-chip (SoC) applications. A compensation scheme is presented that provides both a fast transient response and full range alternating current (AC) stability from 0- to 50-mA load current even if the output load is as high as 100 pF. The 2.8-V capacitorless LDO voltage regulator with a power supply of 3 V was fabricated in a commercial 0.35-mum CMOS technology, consuming only 65 muA of ground current with a dropout voltage of 200 mV. Experimental results demonstrate that the proposed capacitorless LDO architecture overcomes the typical load transient and ac stability issues encountered in previous architectures. View full abstract»

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  • Adaptive Noise Cancellation Techniques in Sigma–Delta Analog-to-Digital Converters

    Publication Year: 2007 , Page(s): 1891 - 1899
    Cited by:  Papers (3)
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (434 KB) |  | HTML iconHTML  

    Adaptive noise cancellation (ANC) techniques that extract a desired signal from background noise have many applications in different engineering disciplines. In ANC, the corrupted signal is passed through a filter that tends to suppress the noise while leaving the original signal unchanged. This paper demonstrates that the adaptive noise cancellation technique can be embedded in the digital signal postprocessing of a sigma-delta analog-to-digital converter and effectively reduces the quantization noise as well as the thermal noise at the output of the converter. The combination of ANC and the noise-shaping technique enable high-resolution analog-to-digital conversion in wideband applications where noise shaping alone cannot provide enough suppression of quantization noise due to the low oversampling ratio. View full abstract»

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  • Novel Process and Temperature-Stable, IDD Sensor for the BIST Design of Embedded Digital, Analog, and Mixed-Signal Circuits

    Publication Year: 2007 , Page(s): 1900 - 1915
    Cited by:  Papers (2)
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (1945 KB) |  | HTML iconHTML  

    This paper proposes a new IDD sensor for built-in self-test (BIST) applications for digital, analog, and mixed-signal circuits. This novel, wide-band, nonintrusive, process and temperature-stable IDD sensor operates up to 230 MHz, which is 2.3X faster than previously proposed designs, and occupies 78.3% less area than another competing design. A BIST utilizing this novel IDD sensor is created and tested on numerous digital circuits, as well as on an op-amp and a mixer, achieving up to 90% fault coverage, while maintaining the performance of the circuit-under-test. The experiments were implemented in 0.18-m TSMC CMOS mixed-signal technology. View full abstract»

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  • Power–Delay–Area–Noise Margin Tradeoffs in Positive-Feedback MOS Current-Mode Logic

    Publication Year: 2007 , Page(s): 1916 - 1928
    Cited by:  Papers (4)
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (1329 KB) |  | HTML iconHTML  

    In this paper, positive feedback source-coupled logic (PFSCL) gates are analyzed from a design point of view. The design space is explored through analytical relationships which relate the gate delay, power consumption and noise margin, which are modeled through a simplified circuit analysis. To be more specific, a simple and accurate model of the noise margin is used to derive a systematic design strategy to size the transistors' aspect ratios ensuring an assigned noise margin for a given bias current. From the knowledge of the transistor sizes, the gate delay is then expressed as a function of the bias current and the supply voltage, both of which define the static power consumption of PFSCL gates, as well as of the logic swing, which determines the noise margin. Therefore, this delay model simply relates the speed performance, the power consumption and the noise margin of PFSCL gates, and accounts for the dependence on the fan-in and fan-out. Extensive SPICE simulations with a 0.18-m CMOS process confirm the adequate accuracy of the analytical models and the validity of the approximations introduced to simplify the analysis, and a practical design example of an equality comparator is also presented. In order to derive clear guidelines to manage the delay-power-noise margin tradeoff, PFSCL gates are analyzed in typical design cases (i.e., design for high speed, low power and power efficiency). For the sake of completeness, the effect of each design parameter on the silicon area occupied by a PFSCL gate is also qualitatively analyzed. The resulting criteria are thus useful to design PFSCL gates without resorting to time-consuming design iterations with a trial and error approach based on simulations. View full abstract»

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  • High-Speed Architecture Design of Tomlinson–Harashima Precoders

    Publication Year: 2007 , Page(s): 1929 - 1937
    Cited by:  Papers (12)  |  Patents (1)
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (490 KB) |  | HTML iconHTML  

    Like decision feedback equalizers (DFEs), Tomlinson-Harashima precoders (TH precoders) contain nonlinear feedback loops, which limit their use for high-speed applications. Unlike in DFEs where the output levels of the nonlinear devices are finite, in TH precoders, theoretically, the output levels of the modulo devices are infinite. Thus, it is difficult to apply look-ahead and pre-computation techniques to pipeline TH precoders, which were successfully applied to pipeline infinite-impulse response (IIR) filters and DFEs in the past. In this paper, three approaches are proposed to design high-speed TH precoders. In the first approach, the traditional block processing technique for DFEs is generalized to the design of high-speed TH precoders. In the second approach, based on the equivalent form of a TH precoder where the precoder can be viewed as an IIR filter with an input equal to the sum of the original input to the TH precoder and a finite-level compensation signal, two high-speed pipelined designs are developed. In the third approach, parallel processing techniques for fast IIR filters are generalized to the design of parallel TH precoders. View full abstract»

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  • Adaptive Beamforming Using Frequency Invariant Uniform Concentric Circular Arrays

    Publication Year: 2007 , Page(s): 1938 - 1949
    Cited by:  Papers (11)
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (1114 KB) |  | HTML iconHTML  

    This paper proposes new adaptive beamforming algorithms for a class of uniform concentric circular arrays (UCCAs) having near-frequency invariant characteristics. The basic principle of the UCCA frequency invariant beamformer (FIB) is to transform the received signals to the phase mode representation and remove the frequency dependence of individual phase modes through the use of a digital beamforming or compensation network. As a result, the far field pattern of the array is electronic steerable and is approximately invariant over a wider range of frequencies than the uniform circular arrays (UCAs). The beampattern is governed by a small set of variable beamformer weights. Based on the minimum variance distortionless response (MVDR) and generalized sidelobe canceller (GSC) methods, new recursive adaptive beamforming algorithms for UCCA-FIB are proposed. In addition, robust versions of these adaptive beamforming algorithms for mitigating direction-of-arrival (DOA) and sensor position errors are developed. Simulation results show that the proposed adaptive UCCA-FIBs converge much faster and reach a considerable lower steady-state error than conventional broadband UCCA beamformers without using the compensation network. Since fewer variable multipliers are required in the proposed algorithms, it also leads to lower arithmetic complexity and faster tracking performance than conventional methods. View full abstract»

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  • Optimal Design of Nearfield Wideband Beamformers Robust Against Errors in Microphone Array Characteristics

    Publication Year: 2007 , Page(s): 1950 - 1959
    Cited by:  Papers (21)
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (2714 KB) |  | HTML iconHTML  

    Nearfield wideband beamformers for microphone arrays have wide applications, such as hands-free telephony, hearing aids, and speech input devices to computers. The existing design approaches for nearfield wideband beamformers are highly sensitive to errors in microphone array characteristics, i.e., microphone gain, phase, and position errors, as well as sound speed errors. In this paper, a robust design approach for nearfield wideband beamformers for microphone arrays is proposed. The robust nearfield wideband beamformers are designed based on the minimax criterion with the worst case performance optimization. The design problems can be formulated as second-order cone programming and be solved efficiently using the well-established polynomial time interior-point methods. Several interesting properties of the robust nearfield wideband beamformers are derived. Numerical examples are given to demonstrate the efficacy of the proposed beamformers in the presence of errors in microphone array characteristics. View full abstract»

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  • Parasitics Realization in State-Space Average-Value Modeling of PWM DC–DC Converters Using an Equal Area Method

    Publication Year: 2007 , Page(s): 1960 - 1967
    Cited by:  Papers (17)
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (473 KB) |  | HTML iconHTML  

    Average-value modeling of pulsewidth-modulation dc-dc converters is often based on the assumption of piecewise-linear waveforms of the circuit variables, whereas considering parasitics introduces waveform nonlinearity and complicates the model derivation. This paper presents a new approach that considers averaging with nonlinear waveforms using the equivalent area method, and proposes a state-space averaged model that is fairly accurate and seamlessly functional in both continuous and discontinuous conduction modes. The resulting average-value model is applicable for large-signal transient studies as well as for linearization and subsequent small-signal analysis. The proposed model is validated with a hardware prototype and a detailed simulation, and is shown to be an improvement over previously established models in the time and frequency domains. View full abstract»

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  • A Repetitive-Based Controller for a Power Factor Precompensator

    Publication Year: 2007 , Page(s): 1968 - 1976
    Cited by:  Papers (18)
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (1651 KB) |  | HTML iconHTML  

    In this paper, a repetitive-based controller for a boost-based power factor precompensator is presented. The controller guarantees voltage regulation with a power factor close to unity, despite of the presence of harmonic distortion in the source voltage and uncertainties in the system parameters. It is shown that the repetitive scheme considered here is, in fact, equivalent to a bank of resonant filters, which has shown to be a useful technique in harmonic compensation. Out of this equivalence, a negative feedback structure is obtained for the repetitive scheme which is aimed for the compensation of odd harmonics only. This is in contrast to usual positive feedback repetitive schemes aimed to compensate for all harmonic components. The repetitive scheme consists on a simple feedback array involving a time delay plus a feedforward path, which is simple to implement. The closed-loop stability analysis of such and infinite-dimensional system is performed appealing to the well-known small gain theorem. Experimental results in a 400-W boost-based power factor compensator (PFC), with a fixed-point digital signal processor (DSP)-based implementation of the proposed controller, are provided to assess the performance of the controlled system. View full abstract»

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  • Super-Resolution Time Delay Estimation in Multipath Environments

    Publication Year: 2007 , Page(s): 1977 - 1986
    Cited by:  Papers (15)
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (571 KB) |  | HTML iconHTML  

    The super-resolution time delay estimation in multipath environment is very important for many applications. Conventional super-resolution approaches can only deal with signals with wideband and flat spectra. In this paper, we propose a novel super-resolution time delay estimation method that can treat signals with narrowband spectra. In our method, the time delay estimation is first transformed into the frequency domain, in which the problem is converted into the parameter estimation of sinusoidal signals with lowpass envelopes. Then a MUSIC-type algorithm taking account of the envelope variation is applied to achieve the super-resolution estimation. Time delay estimation in active and passive systems are considered. Simulation results confirm that the proposed estimators provide better performance than the classical correlation approach and the conventional MUSIC algorithm for separating closely spaced signals with narrowband spectra. View full abstract»

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  • Design Methodology for Domain Specific Parameterizable Particle Filter Realizations

    Publication Year: 2007 , Page(s): 1987 - 2000
    Cited by:  Papers (6)
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (1306 KB) |  | HTML iconHTML  

    This paper presents a reconfigurable particle filter design methodology for a real-time bearings-only tracking application. The methodology provides the capability of selecting a single particle filter from multiple particle filter realizations with maximum resource sharing. The autonomous buffer controller mechanism for the architecture ensures correct operation of the particle filters. Parameter adaptation and algorithm reconfiguration can be accomplished with negligible reconfiguration overhead through buffer controllers and a set of switches for transforming dataflow structures such that any desired particle filter can be implemented. Two target particle filters, sample importance resample filter (SIRF) and Gaussian particle filter (GPF), are realized using field programmable gate array (FPGA) based on the proposed methodology. However, the architecture can be extended for a wide range of particle filters with different sets of dynamics. This paper successfully demonstrates that implementation of a domain specific processor for particle filters is feasible with performance that is much higher than that of commercially available digital signal processors (DSPs). View full abstract»

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  • Closed-Form RC and RLC Delay Models Considering Input Rise Time

    Publication Year: 2007 , Page(s): 2001 - 2010
    Cited by:  Papers (8)
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (643 KB) |  | HTML iconHTML  

    The Elmore delay model is the most popular and efficient delay model used for analytical delay estimation. Closed-form delay formulas are useful for circuit design, timing-driven physical design, synthesis, and optimization. As signal rise time becomes faster and the line resistance becomes smaller from copper technology, the significance of inductance increases. Both RC and RLC delays are a strong function of signal rise time. We propose a novel and efficient delay modeling method based on nondimensionalization to consider finite input rise time as an improvement over the Elmore's approach. To further improve the accuracy of the delay model, a new correction method, effective distance correction factor (EDCF), is proposed to consider resistive shielding of downstream capacitance. EDCF can be used to correct the delays for both RC and RLC tree structures. The proposed delay modeling method was applied to a number of nets selected from an integrated circuit (IC) design, and the delay estimation results were compared with HSPICE simulations. The new delay model retains the efficiency and simplicity of the Elmore delay model with significantly improved accuracy. View full abstract»

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  • A Method for Reduced Finite Precision Effects in Parallel Filtering Echo Cancellation

    Publication Year: 2007 , Page(s): 2011 - 2018
    Cited by:  Papers (1)
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (649 KB) |  | HTML iconHTML  

    The two-path algorithm is an adaptive filter algorithm based on a parallel filter structure, which has been found to be useful for line echo cancellation as well as for acoustic echo cancellation. It is well known that in finite precision arithmetic, the adaptation process of adaptive algorithms can be reduced or even halted due to finite precision effects. This paper proposes a variant of the two-path scheme where the effects of quantization are reduced, without any significant increase in complexity. The improvement is shown by simulations using bandlimited flat spectrum noise as well as real speech signals. View full abstract»

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  • Adaptive Tracking Control of Chaotic Systems With Applications to Synchronization

    Publication Year: 2007 , Page(s): 2019 - 2029
    Cited by:  Papers (34)
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (848 KB) |  | HTML iconHTML  

    We address the problem of controlled synchronization of a class of uncertain chaotic systems. Our approach follows techniques of adaptive tracking control and identification of dynamic systems from recent developments of control theory. In particular, we use new notions of the so-called property of persistency of excitation - known to be sufficient and necessary for parameter estimation - to construct adaptive algorithms that ensure perfect tracking/synchronization and parameter estimation of chaotic systems with parameter uncertainty. Our theoretical findings are supported by particular examples and simulation studies on systems such as the Lorenz and Rossler oscillators and the Duffing equation. View full abstract»

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  • RSNS-to-Binary Conversion

    Publication Year: 2007 , Page(s): 2030 - 2043
    Cited by:  Papers (4)  |  Patents (1)
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (721 KB) |  | HTML iconHTML  

    The robust symmetrical number system (RSNS) is a symmetrical number system formed such that only one element in each RSNS vector changes between code transitions. This integer Gray-code property makes the RSNS useful in analog-to-digital converters (ADC), direction finding antenna architectures and electro-optical ADCs since it eliminates any encoding errors that can occur when the input signal lies about any code transition point. One of the fundamental difficulties in a hardware application of the RSNS, such as an ADC, is the conversion of the RSNS residue vectors into a more convenient representation such as a binary number. By exploiting the one-to-one correspondence between the RSNS and the residue number system, an efficient process for conversion of the symmetrical residues is formed. The conversion process presented in this paper produces a hardware implementation that is at least an order of magnitude smaller in terms of transistor count than read-only-memory conversion methods, and is easily pipelined to achieve fast conversion speeds. View full abstract»

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  • A Digital Receiver Architecture for Bluetooth in 0.25- μm CMOS Technology and Beyond

    Publication Year: 2007 , Page(s): 2044 - 2053
    Cited by:  Papers (1)
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (1685 KB) |  | HTML iconHTML  

    A digital receiver architecture for short-range communications systems like Bluetooth is presented. The architecture is tailored to a highly integrated Bluetooth single-chip integrated circuit (IC) and can easily be adapted to other communications systems using a Gaussian frequency-shift keying (GFSK ) modulation scheme. The single-chip IC integrates the complete digital baseband and radio frequency (RF) functionality on a single die and is realized in a 0.25-mum complementary metal-oxide-semiconductor (CMOS) technology targeted for cost efficiency. The superior performance of this digital receiver architecture compared to the state-of-the-art short-range communications receivers is shown. Simulation and measurement results are presented showing a receiver sensitivity of 87 dBm and excellent co-channel and adjacent channel interference performance. View full abstract»

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  • Analytic Solution to the Photovoltaic Maximum Power Point Problem

    Publication Year: 2007 , Page(s): 2054 - 2060
    Cited by:  Papers (53)  |  Patents (25)
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (317 KB) |  | HTML iconHTML  

    Photovoltaic (PV) power has been successfully used for over five decades. Whether in dc or ac form, photovoltaic cells provide power for systems in many applications on earth and space. Its principles of operation are therefore well understood, and circuit equivalents have been developed that accurately model the nonlinear relationship between the current and voltage of a photovoltaic cell. With the improved efficiencies of power electronics converters, it is now possible to operate photovoltaic system about its maximum power point (MPP) in order to improve the overall system efficiency. Hitherto, this problem has been tackled using tracking (MPPT) algorithms that iteratively find the point of maximum power and respond to changes in solar irradiance accordingly. A mathematical manipulation that uses the mean value theorem is presented here that provides the analytic solution of a point in a close neighborhood of the MPP. It is thoroughly proved that this point is enclosed in a ball of small radius that also contains the MPP and therefore can practically be considered as the MPP. Since the solution is analytic, no iterative schemes are necessary, and only a periodic measurement is required to adjust to changes in solar irradiance. A circuit is implemented that shows the validity of the theory and the accuracy of the solution. View full abstract»

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  • A New Constructive Procedure for 2-D Coprime Realization in Fornasini–Marchesini Model

    Publication Year: 2007 , Page(s): 2061 - 2069
    Cited by:  Papers (12)
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (518 KB) |  | HTML iconHTML  

    This paper presents a new constructive procedure for coprime realization of 2-D systems by means of the Fornasini-Marchesini second (FM-II) local state-space model. By exploiting the structural properties of an FM-II model realization, the proposed method can reduce the upper bound on the realization order for a large class of 2-D systems to about half of that obtained by the realization procedure given by the authors recently. It is also revealed that the new procedure is able to obtain minimal realizations for a much larger class of 2-D systems than the existing methods. Nontrivial examples are presented to illustrate the basic ideas and the effectiveness of the proposed method. View full abstract»

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  • Delay-Dependent H Control and Filtering for Uncertain Markovian Jump Systems With Time-Varying Delays

    Publication Year: 2007 , Page(s): 2070 - 2077
    Cited by:  Papers (124)
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (433 KB) |  | HTML iconHTML  

    This paper deals with the problems of delay-dependent robust Hinfin control and filtering for Markovian jump linear systems with norm-bounded parameter uncertainties and time-varying delays. In terms of linear matrix inequalities, improved delay-dependent stochastic stability and bounded real lemma (BRL) for Markovian delay systems are obtained by introducing some slack matrix variables. The conservatism caused by either model transformation or bounding techniques is reduced. Based on the proposed BRL, sufficient conditions for the solvability of the robust Hinfin control and Hinfin filtering problems are proposed, respectively. Dynamic output feedback controllers and full-order filters, which guarantee the resulting closed-loop system and the error system, respectively, to be stochastically stable and satisfy a prescribed Hinfin performance level for all delays no larger than a given upper bound, are constructed. Numerical examples are provided to demonstrate the reduced conservatism of the proposed results in this paper. View full abstract»

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  • Robust Dichotomy Analysis and Synthesis With Application to an Extended Chua's Circuit

    Publication Year: 2007 , Page(s): 2078 - 2086
    Cited by:  Papers (2)
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (658 KB) |  | HTML iconHTML  

    Dichotomy, or monostability, is one of the most important properties of nonlinear dynamic systems. For a dichotomous system, the solution of the system is either unbounded or convergent to a certain equilibrium, thus periodic or chaotic states cannot exist in the system. In this paper, a new methodology for the analysis of dichotomy of a class of nonlinear systems is proposed, and a linear matrix inequality (LMI)-based criterion is derived. The results are then extended to uncertain systems with real convex polytopic uncertainties in the linear part, and the LMI representation for robust dichotomy allows the use of parameter-dependent Lyapunov function. Based on the results, a dynamic output feedback controller guaranteeing robust dichotomy is designed, and the controller parameters are explicitly expressed by a set of feasible solutions of corresponding linear matrix inequalities. An extended Chua's circuit with two nonlinear resistors is given at the end of the paper to demonstrate the validity and applicability of the proposed approach. It is shown that by investigating the convergence of the bounded oscillating solutions of the system, our results suggests a viable and effective way for chaos control in nonlinear circuits. View full abstract»

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  • Theoretical Design and Circuit Implementation of Multidirectional Multi-Torus Chaotic Attractors

    Publication Year: 2007 , Page(s): 2087 - 2098
    Cited by:  Papers (25)
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (2811 KB) |  | HTML iconHTML  

    This paper introduces a novel fourth-order double-torus chaotic circuit. Based on this basic circuit, a systematic theoretical design approach is proposed for generating 1-Dn torus, 2-D n times m-torus, 3-D n times m times I torus, and 4-D n times m times l times p torus chaotic attractors. This is the first autonomous circuit reported in the literature for generating multidirectional multi-torus (MDMT) chaotic attractors. The dynamical behaviors of these MDMT chaotic systems are further investigated, including equilibrium points, bifurcations, Lyapunov exponents, and Poincare maps. Theoretical analysis shows that the MDMT chaotic attractors can be generated by switching and displacing a basic linear circuit. Finally, a block circuit diagram is designed for hardware implementation of the MDMT chaotic attractors. This is also the first time in the literature to experimentally verify a maximal 1-D 20-torus, a maximal 2-D 5 times 5 torus, and a maximal 4-D 5 times 5 times 3 times 3 torus chaotic attractors. View full abstract»

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  • Generalized Multivariate Rectangular Matrix PadÉ-Type Approximants

    Publication Year: 2007 , Page(s): 2099 - 2105
    Cited by:  Papers (2)
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (263 KB) |  | HTML iconHTML  

    A new method for the construction of generalized multivariate rectangular matrix Pade-type approximants on a rectangular grid is introduced in this paper, by choosing an arbitrary monic bivariate polynomial as the generating one of the approximant. We discuss their several typical important properties and study the connection between bivariate rectangular matrix Pade-type approximants and Pade approximants. The arguments given in detail in two variables can extend directly to the case of d variables (d ges 2). View full abstract»

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Aims & Scope

The theory, analysis, design, and practical implementations of circuits, and the application of circuit techniques to systems and to signal processing.

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Meet Our Editors

Editor-in-Chief
Shanthi Pavan
Indian Institute of Technology, Madras