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IEEE Transactions on Very Large Scale Integration (VLSI) Systems

Issue 10 • Date Oct. 2007

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Displaying Results 1 - 16 of 16
  • Table of contents

    Publication Year: 2007, Page(s): C1
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  • IEEE Transactions on Very Large Scale Integration (VLSI) Systems publication information

    Publication Year: 2007, Page(s): C2
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  • Guest Editorial Special Section on System-on-Chip Integration: Challenges and Implications

    Publication Year: 2007, Page(s):1065 - 1066
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  • Utilizing Redundancy for Timing Critical Interconnect

    Publication Year: 2007, Page(s):1067 - 1080
    Cited by:  Papers (1)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (888 KB) | HTML iconHTML

    Conventionally, the topology of signal net routing is almost always restricted to Steiner trees, either unbuffered or buffered. However, introducing redundant paths into the topology (which leads to non-tree) may significantly improve timing performance as well as tolerance to open faults and variations. These advantages are particularly appealing for timing critical net routings in nanoscale VLSI... View full abstract»

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  • 3-D Topologies for Networks-on-Chip

    Publication Year: 2007, Page(s):1081 - 1090
    Cited by:  Papers (117)  |  Patents (1)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (857 KB) | HTML iconHTML

    Several interesting topologies emerge by incorporating the third dimension in networks-on-chip (NoC). The speed and power consumption of 3D NoC are compared to that of 2D NoC. Physical constraints, such as the maximum number of planes that can be vertically stacked and the asymmetry between the horizontal and vertical communication channels of the network, are included in speed and power consumpti... View full abstract»

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  • Applying CDMA Technique to Network-on-Chip

    Publication Year: 2007, Page(s):1091 - 1100
    Cited by:  Papers (17)  |  Patents (15)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (576 KB) | HTML iconHTML

    The issues of applying the code-division multiple access (CDMA) technique to an on-chip packet switched communication network are discussed in this paper. A packet switched network-on-chip (NoC) that applies the CDMA technique is realized in register-transfer level (RTL) using VHDL. The realized CDMA NoC supports the globally-asynchronous locally-synchronous (GALS) communication scheme by applying... View full abstract»

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  • An On-Chip Multichannel Waveform Monitor for Diagnosis of Systems-on-a-Chip Integration

    Publication Year: 2007, Page(s):1101 - 1110
    Cited by:  Papers (14)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (1508 KB) | HTML iconHTML

    An on-chip multichannel waveform monitoring technique enhances built-in test and diagnostic capabilities of systems- on-a-chip (SoC) integration. The proposed multichannel monitor includes multiple probing front-end modules and a single shared waveform acquisition kernel that consists of an incremental variable step delay generator and an incremental reference voltage generator, featuring adaptive... View full abstract»

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  • Simultaneous On-Chip Bus Synthesis and Voltage Scaling Under Random On-Chip Data Traffic

    Publication Year: 2007, Page(s):1111 - 1124
    Cited by:  Papers (3)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (976 KB) | HTML iconHTML

    This paper presents a statistical approach to synthesize an energy conscious the optimal bus width and the number of buses. The slack is exploited to maximize bus sharing and to reduce energy consumption by simultaneously scaling the voltage during the synthesis of on-chip communication bus. An assumption for bus synthesis is that a system has been partitioned and mapped onto the appropriate modul... View full abstract»

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  • A Scalable Dual-Clock FIFO for Data Transfers Between Arbitrary and Haltable Clock Domains

    Publication Year: 2007, Page(s):1125 - 1134
    Cited by:  Papers (23)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (1538 KB) | HTML iconHTML

    A robust, scalable, and power efficient dual-clock first-input first-out (FIFO) architecture which is useful for transferring data between modules operating in different clock domains is presented. The architecture supports correct operation in applications where multiple clock cycles of latency exist between the data producer, FIFO, and the data consumer; and with arbitrary clock frequency change... View full abstract»

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  • ProTaR: An Infrastructure IP for Repairing RAMs in System-on-Chips

    Publication Year: 2007, Page(s):1135 - 1143
    Cited by:  Papers (27)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (991 KB) | HTML iconHTML

    Complex system-on-a-chip (SOC) designs usually consist of many memory cores. Efficient yield-enhancement techniques thus are required for the memory cores in SOCs. This paper presents an infrastructure intelligent property (IIP) for testing, diagnosing, and repairing multiple memory cores in SOCs. The proposed IIP can perform parallel testing for multiple memories, and serial diagnosis or repair f... View full abstract»

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  • Wafer-Level Modular Testing of Core-Based SoCs

    Publication Year: 2007, Page(s):1144 - 1154
    Cited by:  Papers (2)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (863 KB) | HTML iconHTML

    Product cost is a major driver in the consumer electronics market, which is characterized by low profit margins and the use of core-based system-on-chip (SoC) designs. Packaging has been recognized as a significant contributor to the product cost for such SoCs. To reduce packaging cost and the test cost for packaged chips, wafer-level testing (wafer sort) is used in the semiconductor industry to s... View full abstract»

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  • DFT Techniques and Automation for Asynchronous NULL Conventional Logic Circuits

    Publication Year: 2007, Page(s):1155 - 1159
    Cited by:  Papers (4)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (1156 KB) | HTML iconHTML

    Conventional automatic test pattern generation (ATPG) algorithms fail when applied to asynchronous NULL convention logic (NCL) circuits due to the absence of a global clock and presence of more state-holding elements, leading to poor fault coverage. This paper presents a design-for-test (DFT) approach aimed at making asynchronous NCL designs testable using conventional ATPG programs. We propose an... View full abstract»

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  • Code Compression for VLIW Embedded Systems Using a Self-Generating Table

    Publication Year: 2007, Page(s):1160 - 1171
    Cited by:  Papers (5)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (1968 KB) | HTML iconHTML

    We propose a new class of methods for VLIW code compression using variable-sized branch blocks with self-generating tables. Code compression traditionally works on fixed-sized blocks with its efficiency limited by their small size. A branch block, a series of instructions between two consecutive possible branch targets, provides larger blocks for code compression. We compare three methods for comp... View full abstract»

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  • Low-Power Limited-Search Parallel State Viterbi Decoder Implementation Based on Scarce State Transition

    Publication Year: 2007, Page(s):1172 - 1176
    Cited by:  Papers (6)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (273 KB) | HTML iconHTML

    In this paper, a low-power Viterbi decoder design based on scarce state transition (SST) is presented. A low complexity algorithm based on a limited search algorithm, which reduces the average number of the add-compare-select computation of the Viterbi algorithm, is proposed and seamlessly integrated with the SST-based decoder. The new decoding scheme has low overhead and facilitates low-power imp... View full abstract»

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  • IEEE Transactions on Very Large Scale Integration (VLSI) Systems society information

    Publication Year: 2007, Page(s): C3
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  • IEEE Transactions on Very Large Scale Integration (VLSI) Systems Information for authors

    Publication Year: 2007, Page(s): C4
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Aims & Scope

Design and realization of microelectronic systems using VLSI/ULSI technologies requires close collaboration among scientists and engineers in the fields of systems architecture, logic and circuit design, chips and wafer fabrication, packaging, testing, and systems applications. Generation of specifications, design, and verification must be performed at all abstraction levels, including the system, register-transfer, logic, circuit, transistor, and process levels. To address this critical area through a common forum, the IEEE Transactions on VLSI Systems was founded.

Full Aims & Scope

Meet Our Editors

Editor-in-Chief

Krishnendu Chakrabarty
Department of Electrical Engineering
Duke University
Durham, NC 27708 USA
Krish@duke.edu