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Computers, IEEE Transactions on

Issue 10 • Date Oct. 2007

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Displaying Results 1 - 20 of 20
  • [Front cover]

    Publication Year: 2007 , Page(s): c1
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  • [Inside front cover]

    Publication Year: 2007 , Page(s): c2
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  • Mixed-Radix Gray Codes in Lee Metric

    Publication Year: 2007 , Page(s): 1297 - 1307
    Cited by:  Papers (3)
    Save to Project icon | Request Permissions | Click to expandAbstract | PDF file iconPDF (1368 KB) |  | HTML iconHTML  

    Gray codes, where two consecutive codewords differ in exactly one position by plusmn1, are given. In a single-radix code, all dimensions have the same base, say, kappa, whereas, in a mixed-radix code, the base in one dimension can be different from the base in another dimension. Constructions of new classes of mixed-radix Gray codes are presented. It is shown how these codes can be used as a basis... View full abstract»

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  • Hardware Complexity of Modular Multiplication and Exponentiation

    Publication Year: 2007 , Page(s): 1308 - 1319
    Cited by:  Papers (4)  |  Patents (2)
    Save to Project icon | Request Permissions | Click to expandAbstract | PDF file iconPDF (4392 KB) |  | HTML iconHTML  

    Large integer modular multiplication (MM) and modular exponentiation (ME) are the foundation of most public-key cryptosystems, specifically RSA, Diffie-Helleman, EIGamal, and the elliptic curve cryptosystems. Thus, MM algorithms have been studied widely and extensively. Most of the work is based on the well-known Montgomery multiplication method and its variants, which require standard multiplicat... View full abstract»

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  • Multioperand Parallel Decimal Adder: A Mixed Binary and BCD Approach

    Publication Year: 2007 , Page(s): 1320 - 1328
    Cited by:  Papers (18)
    Save to Project icon | Request Permissions | Click to expandAbstract | PDF file iconPDF (2342 KB) |  | HTML iconHTML  

    Decimal arithmetic has been revived in recent years due to the large amount of data in commercial applications. We consider the problem of multioperand parallel decimal addition with an approach that uses binary arithmetic, suggested by the adoption of binary-coded decimal (BCD) numbers. This involves corrections in order to obtain the BCD result or a binary-to-decimal (BD) conversion. We adopt th... View full abstract»

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  • Combinatorial Reverse Auction based Scheduling in Multi-Rate Wireless Systems

    Publication Year: 2007 , Page(s): 1329 - 1341
    Cited by:  Papers (9)
    Save to Project icon | Request Permissions | Click to expandAbstract | PDF file iconPDF (2268 KB) |  | HTML iconHTML  

    Opportunistic scheduling algorithms are effective in exploiting channel variations and maximizing system throughput in multirate wireless networks. However, most scheduling algorithms ignore the per-user quality-of-service (QoS) requirements and try to allocate resources (for example, the time slots) among multiple users. This leads to a phenomenon commonly referred to as the ... View full abstract»

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  • Enlarging Instruction Streams

    Publication Year: 2007 , Page(s): 1342 - 1357
    Cited by:  Papers (2)
    Save to Project icon | Request Permissions | Click to expandAbstract | PDF file iconPDF (2734 KB) |  | HTML iconHTML  

    Web applications are widely adopted and their correct functioning is mission critical for many businesses. At the same time, Web applications tend to be error prone and implementation vulnerabilities are readily and commonly exploited by attackers. The design of countermeasures that detect or prevent such vulnerabilities or protect against their exploitation is an important research challenge for ... View full abstract»

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  • Utility Accrual Real-Time Scheduling Under the Unimodal Arbitrary Arrival Model with Energy Bounds

    Publication Year: 2007 , Page(s): 1358 - 1371
    Cited by:  Papers (8)
    Save to Project icon | Request Permissions | Click to expandAbstract | PDF file iconPDF (2026 KB) |  | HTML iconHTML  

    In this paper, we consider timeliness and energy optimization in battery-powered dynamic embedded real-time systems, which must remain functional during an operation/mission with a bounded energy budget. We consider application activities that are subject to time/utility function time constraints, statistical assurance requirements on timeliness behavior, and an energy budget which cannot be excee... View full abstract»

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  • Exact Fault-Sensitive Feasibility Analysis of Real-Time Tasks

    Publication Year: 2007 , Page(s): 1372 - 1386
    Cited by:  Papers (13)
    Save to Project icon | Request Permissions | Click to expandAbstract | PDF file iconPDF (1774 KB) |  | HTML iconHTML  

    In this paper, we consider the problem of checking the feasibility of a set of n real-time tasks while provisioning for timely recovery from (at most) k transient faults. We extend the well-known processor demand approach to take into account the extra overhead that may be induced by potential recovery operations under earliest-deadline-first scheduling. We develop a necessary and sufficient test ... View full abstract»

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  • Integrated Row and Column Rerouting for Reconfiguration of VLSI Arrays with Four-Port Switches

    Publication Year: 2007 , Page(s): 1387 - 1400
    Cited by:  Papers (14)
    Multimedia
    Save to Project icon | Request Permissions | Click to expandAbstract | PDF file iconPDF (4161 KB) |  | HTML iconHTML  

    This paper deals with the issue of developing efficient algorithms for reconfiguring two-dimensional VLSI arrays linked by four-port switches in the presence of faulty processing elements (PEs). The proposed algorithm reroutes the arrays with faults in both row and column directions at the same time. Unlike previous work, the compensation technique to replace the faulty PE is not restricted to the... View full abstract»

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  • Automatic Verification of Arithmetic Circuits in RTL Using Stepwise Refinement of Term Rewriting Systems

    Publication Year: 2007 , Page(s): 1401 - 1414
    Cited by:  Papers (8)
    Save to Project icon | Request Permissions | Click to expandAbstract | PDF file iconPDF (2450 KB) |  | HTML iconHTML  

    This paper presents a novel technique for proving the correctness of arithmetic circuit designs described at the register transfer level (RTL). The technique begins with the automatic translation of circuits from a Verilog RTL description into a term rewriting system (TRS). We prove the correctness of the designs via an equivalence proof between TRSs for the implementation circuit design and a muc... View full abstract»

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  • Solution and Optimization of Systems of Pseudo-Boolean Constraints

    Publication Year: 2007 , Page(s): 1415 - 1424
    Cited by:  Papers (4)  |  Patents (5)
    Save to Project icon | Request Permissions | Click to expandAbstract | PDF file iconPDF (2619 KB) |  | HTML iconHTML  

    Optimized solvers for the Boolean satisfiability (SAT) problem have many applications in areas such as hardware and software verification, FPGA routing, planning, and so forth. Further uses are complicated by the need to express "counting constraints" in conjunctive normal form (CNF). Expressing such constraints by pure CNF leads to more complex SAT instances. Alternatively, those constraints can ... View full abstract»

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  • Can-Follow Concurrency Control

    Publication Year: 2007 , Page(s): 1425 - 1430
    Cited by:  Papers (2)
    Save to Project icon | Request Permissions | Click to expandAbstract | PDF file iconPDF (279 KB) |  | HTML iconHTML  

    Can-follow concurrency control permits a transaction to read (write) an item write-locked (read-locked) by another transaction with almost no delays. By combining the merits of 2PL and 2V2PL, this approach mitigates the lock contention not only between update and read-only transactions, but also between update and update transactions. View full abstract»

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  • Early Analysis of Fault-based Attack Effects in Secure Circuits

    Publication Year: 2007 , Page(s): 1431 - 1434
    Cited by:  Papers (13)  |  Patents (1)
    Save to Project icon | Request Permissions | Click to expandAbstract | PDF file iconPDF (395 KB) |  | HTML iconHTML  

    Security often relies on functions implemented in hardware. But, various types of attacks have been developed, in particular, fault-based attacks allowing a hacker to observe abnormal behaviors from which secret data can be inferred. Analyzing very early, during a circuit design, the potential impact of faults therefore becomes necessary to avoid security flaws. Dependability analysis environments... View full abstract»

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  • Subquadratic Computational Complexity Schemes for Extended Binary Field Multiplication Using Optimal Normal Bases

    Publication Year: 2007 , Page(s): 1435 - 1437
    Cited by:  Papers (15)
    Save to Project icon | Request Permissions | Click to expandAbstract | PDF file iconPDF (335 KB) |  | HTML iconHTML  

    Based on a recently proposed Toeplitz matrix-vector product approach, a subquadratic computational complexity scheme is presented for multiplications in binary extended finite fields using type I and II optimal normal bases. View full abstract»

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  • In this issue - Technically

    Publication Year: 2007 , Page(s): 1438
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    Freely Available from IEEE
  • In this issue - Technically

    Publication Year: 2007 , Page(s): 1439
    Save to Project icon | Request Permissions | PDF file iconPDF (41 KB)  
    Freely Available from IEEE
  • 180,000 aritlces in the IEEE Computer Society Digital Library [advertisement]

    Publication Year: 2007 , Page(s): 1440
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  • TC Information for authors

    Publication Year: 2007 , Page(s): c3
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  • [Back cover]

    Publication Year: 2007 , Page(s): c4
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Aims & Scope

The IEEE Transactions on Computers is a monthly publication with a wide distribution to researchers, developers, technical managers, and educators in the computer field.

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Meet Our Editors

Editor-in-Chief
Paolo Montuschi
Politecnico di Torino
Dipartimento di Automatica e Informatica
Corso Duca degli Abruzzi 24 
10129 Torino - Italy
e-mail: pmo@computer.org