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Device and Materials Reliability, IEEE Transactions on

Issue 2 • Date June 2007

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Displaying Results 1 - 25 of 33
  • [Front cover]

    Publication Year: 2007 , Page(s): C1
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    Freely Available from IEEE
  • IEEE Transactions on Device and Materials Reliability publication information

    Publication Year: 2007 , Page(s): C2
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    Freely Available from IEEE
  • Table of contents

    Publication Year: 2007 , Page(s): 213 - 214
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    Freely Available from IEEE
  • Introduction to the Special Issue on 2006 International Integrated Reliability Workshop (IIRW)

    Publication Year: 2007 , Page(s): 215 - 216
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    Freely Available from IEEE
  • HCI Lifetime Correction Based on Self-Heating Characterization for SOI Technology

    Publication Year: 2007 , Page(s): 217 - 224
    Cited by:  Papers (1)
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (788 KB) |  | HTML iconHTML  

    Self-heating (SH) effects, which were observed during the development of silicon-on-insulator (SOI) technology for high-performance circuits, raise questions concerning the validity of the extrapolation method used for hot carrier injection (HCI). In this paper, we propose a new methodology for lifetime prediction based on DC HCI stress for SOI technology. The SH is quantified using coupled DC HCI stress and gate resistance measurements for different transistor widths. Then, the degradation part due to SH is removed, enabling accurate HCI lifetime prediction when SH effects are present. View full abstract»

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  • The Energy-Driven Hot-Carrier Degradation Modes of nMOSFETs

    Publication Year: 2007 , Page(s): 225 - 235
    Cited by:  Papers (35)
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (643 KB) |  | HTML iconHTML  

    In this paper, we confirm that the energy is the driving force of hot-carrier effects. In high-energy long-channel case, the energy-driven paradigm allows to retrieve lucky electron model-like equations although the explanations are different. When the energy is lowered, high-energy electrons generated by electron-electron scattering become the dominant contribution to the degradation. Finally, for even lower energy, multiple vibrational excitation mechanism starts taking the lead. View full abstract»

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  • Use of Resistance-Evolution Dynamics During Electromigration to Determine Activation Energy on Single Samples

    Publication Year: 2007 , Page(s): 236 - 241
    Cited by:  Papers (8)
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (1343 KB) |  | HTML iconHTML  

    In this paper, we present an analysis of resistance change events that are occurring during the degradation of interconnects. The events analyzed are the following: 1) a step jump in resistance and 2) a subsequent progressive linear increase of resistance. We first find that the height of the step is correlated with time to fail. We show that the occurrence of a step is likely due to the vertical growth of a void, and the variation of the resistance-step amplitude is due to the variation of the length of the void from sample to sample. We then find that resistance-increase rate of the progressive part is correlated with copper drift velocity. Thus, we show that it is possible to determine an activation energy on every sample, which is performing temperature change during the progressive part of the resistance increase. View full abstract»

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  • Impact of TiN Plasma Post-Treatment on Alumina Electron Trapping

    Publication Year: 2007 , Page(s): 242 - 251
    Cited by:  Papers (4)
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (1528 KB) |  | HTML iconHTML  

    Three-dimensional architecture appears today to be essential for the next high-density metal-insulator-metal (MIM) capacitor generation. Thus, the classical physical vapor deposition method usually used for the electrode deposition must be replaced by more conformal deposition methods, like chemical vapor deposition (CVD) method. In this paper, trapping phenomenon of MIM capacitors using CVD-TiN for electrodes and atomic layer deposition Al2O3 for insulator is studied, when integrated in planar and in 3-D MIM devices. In particular, we demonstrate the correlation between the plasma post-treatment (PT) applied to the CVD-TiN layer to ensure its low resistivity and the charge trapping in the alumina. Moreover, while applying the Di Maria method to those MIM structures, we demonstrate that charges trapped are electrons, which are located near the metal/insulator interfaces. Based on previous paper, an explanation of the origin of this trapping phenomenon is also proposed. Finally, we demonstrate that the plasma PT does not penetrate correctly into the trenches, suggesting that CVD method for the TiN electrode deposition is not suitable for high-aspect-ratio 3-D devices. View full abstract»

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  • Real-Time Investigation of Conduction Mechanism With Bias Stress in Silica-Based Intermetal Dielectrics

    Publication Year: 2007 , Page(s): 252 - 258
    Cited by:  Papers (6)
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (457 KB) |  | HTML iconHTML  

    The real-time conduction mechanism during bias stress of three silica-based intermetal dielectrics in Cu damascene structures was investigated. High-frequency capacitance and I-V measurements were intermittently inserted into the process of bias stress to monitor the conduction mechanism change with time. All experiments show that the capacitance is constant, and the I-V curve slope decreases with bias stress and converges to half of the initial value. Based on an extended Frenkel-Poole model with compensation effects, we propose that the changes of the acceptor/donor densities in the dielectrics result in the apparent I-V curve slope evolution, but the dominant conduction mechanism is always bulk controlled. View full abstract»

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  • Constant-Current Stressing of SiCr-Based Thin-Film Resistors: Initial “Wearout” Investigation

    Publication Year: 2007 , Page(s): 259 - 269
    Cited by:  Papers (5)
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (1366 KB) |  | HTML iconHTML  

    We have started an investigation of the ldquowearoutrdquo characteristics of two of our thin-film resistor processes as a part of a product and process transfer. Our goals are the following: 1) to find out what happens to these resistors under accelerated stress and define ldquofailure;rdquo 2) to compare results between ldquoequivalentrdquo resistor films that are independently developed in two of our internal fabs; and 3) to generate better reliability-based design rules as a function of current density, temperature, and resistor geometry. We have characterized the changes in resistance and temperature coefficient of resistivity as a result of accelerated to highly accelerated test conditions, using thermal and constant-current stresses, and determined activation energies for some of these changes. We have found that we can produce resistance increases and resistance decreases, depending on resistor process and stress levels, with an activation energy of about 1 eV for resistance increase for one of the resistor process types at one fabrication site and an activation energy of about 3 eV for the resistance decrease for the other three process type and fabrication-site combinations. View full abstract»

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  • Constant-Current Wafer-Level Electromigration Test: Normalization of Data for Production Monitoring

    Publication Year: 2007 , Page(s): 270 - 277
    Cited by:  Papers (2)
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (829 KB) |  | HTML iconHTML  

    Reliability monitoring is an important part of process control in high-volume production. For metallization, a wafer-level electromigration (WL-EM) test is usually the method of choice to get a good indication of process variation. Different WL-EM methods have been reported, including a constant current method, the SWEAT test, the isothermal test, and the breakdown energy of metal test. The method used in this paper uses the ramping procedure for the isothermal test to achieve the target temperature, but then hold the current constant without feedback correction once the target temperature has been achieved. We present practical normalization procedures to ensure an appropriate wafer-to-wafer comparison that is independent of variation in cross-sectional area as well as of the initial resistance spread. The measurements were performed on a commercially available 200-mm multiside probe station using custom software to implement the current ramp and resistance measurement. Test conditions were achieved through Joule heating; the test structures used were 800-mum-long single lines (no vias) in metal 1 to metal 3, varying in width from 0.14 to 10 mum. Due to variations in the hardware and in the temperature coefficient of resistance (TCR), several normalization steps (described below) were necessary in demonstrating reasonable and expected trends in the data. Results of the analysis suggest that the appropriate value for the current density exponent for this test methodology is two, and they also verify that the TCR varies with linewidth, decreasing as linewidth decreases. View full abstract»

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  • TDDB Data Generation for Fast Lifetime Projections Based on V-Ramp Stress Data

    Publication Year: 2007 , Page(s): 278 - 284
    Cited by:  Papers (8)
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (485 KB) |  | HTML iconHTML  

    Reduced failure rates required by the industry lead to increased costs and time loss for the chip manufacturer since the efforts for continuous process improvements, qualification, screening, and increased test coverage are generally not paid by the customer. However, related costs can be reduced by improved/accelerated reliability testing methods and an approach to a knowledge-based and application-specific qualification and process monitoring strategy. One example of saving time (and costs) during gate oxide reliability testing is given in this paper, showing that time-dependent dielectric breakdown (TDDB) data for lifetime extrapolation and quality assessment can be generated from linear ramped voltage test (RVT) data with high accuracy. Given the parameter of the RVT stress profile, the concept of equivalence is successfully applied to convert stress time data at each ramp stress level to corresponding accumulated equivalent ages at any one stress level. Taking into account these ages until breakdown, failure probabilities with the model parameters of the stress-life relationship being the only fitting parameters can directly be computed and converted to TDDB failure distributions. View full abstract»

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  • Systematic Study of the Dopant-Dependent Properties of Electrically Programmable Fuses With Silicided Poly-Si Links Through a Series of I– V Measurements

    Publication Year: 2007 , Page(s): 285 - 297
    Cited by:  Papers (1)  |  Patents (15)
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (1320 KB) |  | HTML iconHTML  

    Electrically programmable/writable fuses (e-fuses) with a Ni-silicided polycrystalline silicon narrow link and fabricated with four doping conditions were studied using two successive I-V measurements. The initial I-V sweeps can change e-fuses into targeted programmed states and display all of the programming processes where the currents change by many orders of magnitude. The second set of I-V curves can show stability and conduction in the programmed states for both bias polarities. Through the series of I-V measurements, the two-step programming with moderate blowing conditions could be reproduced and studied systematically. The programming processes of incompletely programmed states, before complete programming (CP), were found to be strongly dependent on the dopant conditions. The origin of the dopant dependency was considered within a simple electrical equivalent circuit model. At least two or three programmed states were identified among the completely programmed states in terms of the characteristic spreads of the final resistance and conduction behavior. The most distinctive currents after CP are similar to those in varistors. The stability of every programmed state is strongly dependent on the dopant conditions. View full abstract»

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  • NiSi Polysilicon Fuse Reliability in 65-nm Logic CMOS Technology

    Publication Year: 2007 , Page(s): 298 - 303
    Cited by:  Papers (3)
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (427 KB) |  | HTML iconHTML  

    The programming characteristics and reliability of NiSi polysilicon fuse fabricated using 65-nm logic complimentary metal-oxide-semiconductor technology were studied. Under optimal programming conditions, high postprogram resistance can be achieved. These well-programmed fuses showed good data retention under unbiased temperature stress test. In order to avoid read disturb of unprogrammed fuses, the read current has to be kept below the threshold for silicide electromigration. View full abstract»

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  • A Quantitative Study of Endurance Characteristics and Its Temperature Dependance of Embedded Flash Memories With 2T-FNFN nor Device Architecture

    Publication Year: 2007 , Page(s): 304 - 309
    Cited by:  Papers (3)
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (845 KB) |  | HTML iconHTML  

    A quantitative study on the endurance of an embedded Flash memory with 2T-FNFN device architecture in a 0.13-mum technology node has been presented in this paper. Physical insights of 2T-FNFN device degradation have been obtained through stressing and characterizing large parallel arrays of flash transistors (with floating gate connected). Experiments are carried out on large random accessible arrays based on the 2T-FNFN cells, at a wide temperature range and with different program/erase (P/E) voltages. An empirical model has been developed to describe the temperature-dependent degradation of the program window. This model fits the experimental data over the whole temperature range, and the endurance performance with single-shot P/E cycles exceeds 1 million cycles. This paper provides a method for flash endurance characterization and modeling. View full abstract»

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  • Influence of Stress-Induced Leakage Current on Reliability of HfSiOx

    Publication Year: 2007 , Page(s): 310 - 314
    Cited by:  Papers (2)
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (443 KB) |  | HTML iconHTML  

    HfSiOx with TiN gate is investigated under substrate injection with respect to stress-induced leakage current (SILC). Most damage caused by electrical stress was found in the high- layer and not in the interface to silicon. Dependent on the application, SILC can exhibit several levels of severity. In pure logic circuits, a large area approximation is sufficient. However, for memory applications, the current increase in small area is important as well. Both contributions are investigated, revealing no lifetime-limiting current increase. With an improved deposition process, SILC can even be suppressed. View full abstract»

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  • Current Instability, Permittivity Variation With Frequency, and Their Relationship in Ta2O5 Capacitor

    Publication Year: 2007 , Page(s): 315 - 323
    Cited by:  Papers (9)
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (367 KB) |  | HTML iconHTML  

    In this paper, Ta2O5 current instability in MIM and MIS capacitors is studied over several sample thicknesses with a current-versus-time measurement and low-frequency dielectric spectroscopy. Three types of phenomena are identified. The first one is attributed to polarization current correlated to flat loss behavior. The second mechanism corresponds to the conduction current identified as a steady state: a unique mechanism, probably a Poole-Frenkel one, is observed on the whole investigated voltage range. Finally, a resistance degradation phenomenon occurs that has been attributed to ionic diffusion in dielectric and follows the space-charge-limited theory. According to physical characterization, a model based on oxygen vacancies migration in the dielectric is suggested. Moreover, according to low-frequency dielectric spectroscopy measurements, it has been identified that the low-frequency loss peak is created by the same defects and is well modeled by the Maxwell-Wagner approach. View full abstract»

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  • The Impact of Drift Implant and Layout Parameters on ESD Robustness for On-Chip ESD Protection Devices in 40-V CMOS Technology

    Publication Year: 2007 , Page(s): 324 - 332
    Cited by:  Papers (6)
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (1376 KB) |  | HTML iconHTML  

    The dependences of drift implant and layout parameters on electrostatic discharge (ESD) robustness in a 40-V CMOS process have been investigated in silicon chips. From the experimental results, the high-voltage (HV) MOSFETs without drift implant in the drain region have better transmission line pulsing (TLP)-measured secondary breakdown current (It2) and ESD robustness than those with drift implant in the drain region. Furthermore, the It2 and ESD level of HV MOSFETs can be increased as the layout spacing from the drain diffusion to polygate is increased. It was also demonstrated that a specific test structure of HV n-type silicon-controlled rectifier (HVNSCR) embedded into HV NMOS without N-drift implant in the drain region has the excellent TLP-measured It2 and ESD robustness. Moreover, due to the different current distributions in HV NMOS and HVNSCR, the dependences of the TLP-measured It2 and human-body-model ESD levels on the spacing from the drain diffusion to polygate are different. View full abstract»

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  • Postbreakdown Conduction in Ultrathin La2 O3 Gate Dielectrics

    Publication Year: 2007 , Page(s): 333 - 339
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (302 KB) |  | HTML iconHTML  

    The evolution of the conduction characteristics of ultrathin lanthanum oxide (La2O3) gate dielectrics that are subjected to constant and ramped electrical stresses was investigated. The samples were obtained by the electron-beam evaporation technique and annealed in situ in ultrahigh vacuum conditions to minimize the formation of an interfacial oxide layer. We have shown that the total current flowing through the device consists of two parallel contributions, where one is associated with direct and Fowler-Nordheim tunneling and the other one is associated with multiple breakdown (BD) path conduction. This latter component is sensitive to the applied stress and evolves from soft BD to diodelike conduction as the degradation proceeds. We analyzed the experimental data in terms of two well-known models for post-BD conduction. The importance of considering series and parallel resistances within these formulations is shown. View full abstract»

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  • GaN-Based Power LEDs With CMOS ESD Protection Circuits

    Publication Year: 2007 , Page(s): 340 - 346
    Cited by:  Papers (9)
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (318 KB) |  | HTML iconHTML  

    A power light-emitting diode (LED) module has been successfully designed and demonstrated by combining GaN-based power LEDs with CMOS electrostatic discharge (ESD) protection circuits through a flip-chip process. It was found that we could enhance the power LED output intensity by 20% by using the flip-chip technology. Lifetimes of flip-chip power LEDs were also found to be better. It was also found that the use of CMOS ESD protection circuits did not degrade the output intensity and lifetime of flip-chip power LEDs. Furthermore, it was found that we could not only significantly enhance the reverse ESD characteristics but could also enhance the positive ESD characteristics of nitride-based LEDs by using the CMOS ESD protection circuits. View full abstract»

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  • A Current Estimation Method for Bias-Temperature Stress of a-Si TFT Device

    Publication Year: 2007 , Page(s): 347 - 350
    Cited by:  Papers (5)
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (455 KB) |  | HTML iconHTML  

    We have studied the time-dependence degradation of ON current of amorphous silicon thin-film transistors (a-Si:H TFTs), which is a function of stress duration, stress temperature, and stress bias. A simple method with stretched-exponential equation and current-voltage function is used to characterize and predict the TFT performance. Bias-temperature stress at different stress voltages has been performed on a-Si:H TFTs. A new method using ON current degradation to analyze TFT device performance is presented, which is different from the conventional threshold-voltage shift method. We have also observed that the beta value in the ON current degradation method compared to the threshold-voltage shift method, with a stretched-exponential stress time, is related to beta~beta0-TST/T0. Finally, we have also used the new equation to evaluate the performance of the gate-driver-on-array circuit in our products. If the limitation of the current for the pull-down device is 1times10-6 A, then the operation time of the pull-down device can be estimated to about 1219 h when key pulled-down TFT is operating at 60degC. View full abstract»

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  • Nanoscale Bias-Annealing Effect in Postirradiated Thin Silicon Dioxide Films Observed by Conductive Atomic Force Microscopy

    Publication Year: 2007 , Page(s): 351 - 355
    Cited by:  Papers (4)
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (214 KB) |  | HTML iconHTML  

    This paper investigated the reliability of thin silicon dioxide (SiO2) subjected to irradiation followed by stress, using conductive atomic force microscopy (C-AFM). The I-V characteristics of localized spots on thin oxide films were measured before and after Co60gamma-ray irradiation. The oxide films were then subjected to a ramped voltage stress simultaneously during the I-V measurements. By taking advantage of a small contact area, we report for the first time the nanoscale postirradiation bias-annealing effect in thin SiO2 film using C-AFM. Based on the number of fluctuating current peaks appearing in the I-V curves of the pre- and posttreatment oxide films, as well as the calculated effective barrier height from the Fowler-Nordheim tunneling theory, we found that the trapped charge in the oxide films, but not the charge at the interface caused by Co60gamma-ray irradiation, can be effectively annealed out by a postirradiation ramped voltage. View full abstract»

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  • Direct Measurement of Electromigration-Induced Stress in Interconnect Structures

    Publication Year: 2007 , Page(s): 356 - 362
    Cited by:  Papers (6)
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (437 KB) |  | HTML iconHTML  

    This paper reports the first direct experimental measurement of electromigration-induced stress in aluminum interconnects, using a series of microrotating stress sensors. The build-up of stress gradients in interconnect metallization, which is concomitant with backstress, has been previously investigated theoretically, but experimental verification using optical or X-ray techniques has proven more difficult. These initial results show a compressive-stress gradient along the line of stress sensors, consistent with that predicted by conventional mass-transport theory. Additionally, these measurements are in qualitative agreement with the mathematical model proposed by Korhonen et al. (1993), with a reduced-stress and increased-diffusion coefficient. These differences are discussed, and the causes postulated. The limited resolution of previous techniques restricts their ability to obtain a detailed characterization, whereas, in principle, this new technique can be scaled to the end of the International Technology Roadmap for Semiconductors. These preliminary findings suggest that the presented technique will provide a valuable tool for the investigation of back-end-of-line interconnect stress in the future. View full abstract»

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  • Theoretical and Experimental Thermal Analysis of InP Ridge Lasers on Submounts and TO Packages

    Publication Year: 2007 , Page(s): 363 - 368
    Cited by:  Papers (2)
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (528 KB) |  | HTML iconHTML  

    We have determined the junction temperatures of laser diodes mounted on ceramic submounts and hermetic transistor-outline (TO) packages using data from wavelength-shift measurement as well as finite-element modeling (FEM). We found that the difference in the junction temperature between chip/submount and chip/submount/TO measured at the free-standing room-temperature condition cannot be used as the reference data for the design of accelerated life-test condition at hot oven. For the free-standing condition, the heat spread from the active region of the chip to the chip substrate, submount, and TO. Hence, there was an additional thermal gradient in the chip/submount/TO arising from the thermal impedance of the TO header. For the oven condition, the heat dissipation via forced convection from the outer surface of the TO was important. Hence, the thermal gradient of the TO resulting from heat conduction became smaller. Using the FEM, we showed that the simulated junction temperature was in close agreement with the experimental value. The heating difference between the chip/submount and chip/submount/TO was smaller at the oven condition than at the free-standing condition. View full abstract»

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  • Investigation of Potassium Contamination in SOI Wafer Using Dynamic SIMS

    Publication Year: 2007 , Page(s): 369 - 372
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (362 KB) |  | HTML iconHTML  

    Mobile ions may cause critical failures in integrated circuits. For silicon-on-insulator (SOI) wafers, the mobile ions affect not only the reliability of back end of the line but also the performance of the transistors. This paper presents a case study of potassium (K) contamination in the SOI wafer using dynamic secondary ion mass spectrometry. The results showed that the presence of K in chemical and mechanical polish slurry contaminated the porous interlayer dielectrics (ILD), penetrating below the surface due to their porous structure. The K contamination has been greatly reduced by capping the porous ILD with a high-density-oxide layer. View full abstract»

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Aims & Scope

IEEE Transactions on Device and Materials Reliability is published quarterly. It provides leading edge information that is critical to the creation of reliable electronic devices and materials, and a focus for interdisciplinary communication in the state of the art of reliability of electronic devices, and the materials used in their manufacture. It focuses on the reliability of electronic, optical, and magnetic devices, and microsystems; the materials and processes used in the manufacture of these devices; and the interfaces and surfaces of these materials.

Full Aims & Scope

Meet Our Editors

Editor-in-Chief
Anthony S. Oates
Taiwan Semiconductor Mfg Co.