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Electron Device Letters, IEEE

Issue 9 • Date Sept. 2007

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Displaying Results 1 - 25 of 26
  • Table of contents

    Publication Year: 2007 , Page(s): C1 - C4
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  • IEEE Electron Device Letters publication information

    Publication Year: 2007 , Page(s): C2
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  • Impact of CF4 Plasma Treatment on GaN

    Publication Year: 2007 , Page(s): 781 - 783
    Cited by:  Papers (9)
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (169 KB) |  | HTML iconHTML  

    We present a systematic study of the impact of CF4 plasma treatment on GaN. It was found that CF4 plasma etches GaN at a slow rate and yields a smooth etched surface. The effect of CF4 plasma on electrical characteristics of GaN metal-semiconductor field-effect-transistor structures shows that the CF4 plasma introduces acceptors into the near surface region of the GaN, which depletes mobile electrons. It was further demonstrated that leakage current of AlGaN/GaN (or GaN) Schottky diodes can be significantly suppressed by proper CF4 plasma treatment. These unique properties of CF4 plasma can be utilized for the advanced processing of GaN transistors. View full abstract»

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  • Silicon Dioxide-Encapsulated High-Voltage AlGaN/GaN HFETs for Power-Switching Applications

    Publication Year: 2007 , Page(s): 784 - 786
    Cited by:  Papers (4)  |  Patents (18)
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (271 KB) |  | HTML iconHTML  

    In this letter, new approach in achieving high breakdown voltages in AlGaN/GaN heterostructure field-effect transistors (HFETs) by suppressing surface flashover using solid encapsulation material is presented. Surface flashover in III-Nitride-based HFETs limits the operating voltages at levels well below breakdown voltages of GaN. This premature gate-drain breakdown can be suppressed by immersing devices in high-dielectric-strength liquids (e.g., Fluorinert); however, such a technique is not practical. In this letter, AlGaN/GaN HFETs encapsulated with PECVD-deposited SiO2 films demonstrated breakdown voltage of 900 V, very similar to that of devices immersed in Fluorinert liquid. Simultaneously, low dynamic ON-resistance of 2.43 mOmega ldr cm2 has been achieved, making the developed AlGaN/GaN HFETs practical high-voltage high-power switches for power-electronics applications. View full abstract»

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  • Hot-Phonon Effect on the Electrothermal Behavior of Submicrometer III-V HEMTs

    Publication Year: 2007 , Page(s): 787 - 789
    Cited by:  Papers (8)
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (147 KB) |  | HTML iconHTML  

    An investigation of the effect of hot phonons on the electrothermal behavior of GaAs- and GaN-based high electron mobility transistors is carried out using both standard isothermal and self-consistent electrothermal Monte Carlo simulations. The influence of the hot-phonon effect is found to be significantly overestimated when the isothermal approximation is used. The full electrothermal simulations highlight the importance of correctly accounting for the internal temperature profiles of the devices: when this is done, the hot-phonon effect itself has relatively little impact on the electronic and thermal response. View full abstract»

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  • Enhanced Hole Mobility and Reliability of Panel Epi-Like Silicon Transistors Using Backside Green Laser Activation

    Publication Year: 2007 , Page(s): 790 - 792
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    The hole mobility and reliability of green continuous-wave laser-crystallized epi-like Si transistors on glass panel substrates were enhanced by source/drain activation by backside green laser irradiation. Green laser energy was scanned uniformly across junctions since the gate structures included no interference, in an attempt to conduct super visible-laser lateral activation. The enhancement was thus explained by the formation of continuous improved epi-like Si microstructures with reduced grain defects and with a barely increased number of interface defects over the entire channel/junction. The hole mobility in such laser-activated devices was as high as 403 cm2 /V.s, which doubles that of thermally activated devices. View full abstract»

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  • Fabrication of Ni Nanocrystal Flash Memories Using a Polymeric Self-Assembly Approach

    Publication Year: 2007 , Page(s): 793 - 796
    Cited by:  Papers (16)  |  Patents (27)
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (434 KB) |  | HTML iconHTML  

    Fabrication of nickel nanocrystal flash memories using a polymeric approach is presented. Heat treatment of the poly (styrene-b-methyl methacrylate) block copolymer with a molecular weight of 67 000 g/mol followed by PMMA removal in an organic solvent created a porous PS film with 20-nm-diameter pores and a total pore density of ~6 times 1010 cm-2. A trilayer pattern-transfer approach was employed in order to solve the metal lift-off issue intertwined with the low aspect ratio block copolymer patterns. As a result, a highly uniform self- assembled array of nickel nanocrystals was attained and utilized for flash memory fabrication. The memory devices demonstrated an unchanged memory window for up to 2 times 105 stressing cycles. View full abstract»

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  • High-Speed InGaP/GaAs p-i-n Photodiodes With Wide Spectral Range

    Publication Year: 2007 , Page(s): 797 - 799
    Cited by:  Papers (5)
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (404 KB) |  | HTML iconHTML  

    By selectively removing the GaAs cap layer on top of the InGaP/GaAs p-i-n photodiodes, a photodiode with high quantum efficiency in the 300-850-nm spectral range was realized. With antireflection coating designed for 850 nm, a quantum efficiency that is higher than 90% in the 420-850-nm range and higher than 70% in the 360-870-nm range was achieved. In addition, the photodiode, exhibiting a dark current smaller than several picoampere, has a 3-dB bandwidth higher than 9.7 GHz at the 850-nm wavelength. Since both high-efficiency and high-speed operation can be achieved, receivers based on such devices are suitable for both the 850- and 650-nm fiber communication systems. View full abstract»

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  • High-Responsivity Photodetector in Standard SiGe BiCMOS Technology

    Publication Year: 2007 , Page(s): 800 - 802
    Cited by:  Papers (10)
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (162 KB) |  | HTML iconHTML  

    For high-speed optoelectronic applications such as fiber-optic data communication systems, photodetectors (PDs) with high responsivity in Si-related processes are required. In this letter, a result of the effort along this line is reported. A novel device named phototransistor PD (PTPD) was realized in a commercial 0.35-mum SiGe BiCMOS technology. The device combines a surface PD (SPD) and a conventional SiGe heterojunction PT (HPT). It was shown that the SPD enhanced light absorption and the PTPD showed significant performance improvement over HPT. Responsivities of 5.2 A/W for an 850-nm light and 9.5 A/W for a 670-nm light were achieved in the PTPD, with floating base and SPD terminals. View full abstract»

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  • Stability of Amorphous-Silicon and Nanocrystalline Silicon Thin-Film Transistors Under DC and AC Stress

    Publication Year: 2007 , Page(s): 803 - 805
    Cited by:  Papers (6)  |  Patents (2)
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (99 KB) |  | HTML iconHTML  

    Bottom-gated n-channel thin-film transistors (TFTs) were fabricated using hydrogenated amorphous-silicon (a-Si:H)/ nanocrystalline silicon (nc-Si:H) bilayers as channel materials, which are deposited by plasma-enhanced chemical vapor deposition at low temperatures. The stability of these devices is investigated under static and dynamic bias stress conditions. For comparison, the stability of a-Si:H and nc-Si:H single-layer TFTs is investigated under similar bias stress conditions. The overall results demonstrate that the a-Si:H/nc-Si:H bilayer TFTs are superior compared with their counterparts of a-Si:H and nc-Si:H TFTs regarding device performance and stability. View full abstract»

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  • A Novel Low-Temperature Polysilicon Thin-Film Transistors With a Self-Aligned Gate and Raised Source/Drain Formed by the Damascene Process

    Publication Year: 2007 , Page(s): 806 - 808
    Cited by:  Papers (4)
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (359 KB) |  | HTML iconHTML  

    In this letter, a novel structure of the polycrystalline silicon thin-film transistors (TFTs) with a self-aligned gate and raised source/drain (RSD) formed by the damascene process has been developed and investigated. Comparing with the conventional coplanar TFT, the proposed RSD TFT has a remarkable lower off-state current (177 to 6.29 nA), and the on/off current ratio is only slightly decreased from 1.71 times 107 to 1.39 times 107. Only four photomasking steps are required. This novel structure is an excellent candidate for further high-performance large-area device applications. View full abstract»

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  • A Novel Nanowire Channel Poly-Si TFT Functioning as Transistor and Nonvolatile SONOS Memory

    Publication Year: 2007 , Page(s): 809 - 811
    Cited by:  Papers (30)
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (285 KB) |  | HTML iconHTML  

    In this letter, a polycrystalline silicon thin-film transistor consisting of silicon-oxide-nitride-oxide-silicon (SONOS) stack gate dielectric and nanowire (NW) channels was investigated for the applications of transistor and nonvolatile memory. The proposed device, which is named as NW SONOS-TFT, has superior electrical characteristics of transistor, including a higher drain current, a smaller threshold voltage (Vth) , and a steeper subthreshold slope. Moreover, the NW SONOS-TFT also can exhibit high program/erase efficiency under adequate bias operation. The duality of both transistor and memory device for the NW SONOS-TFT can be attributed to the trigate structure and channel corner effect. View full abstract»

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  • Gate Voltage Dependence of MOSFET 1/f Noise Statistics

    Publication Year: 2007 , Page(s): 812 - 814
    Cited by:  Papers (5)
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (145 KB) |  | HTML iconHTML  

    In this letter, we present experimental and theoretical analysis of the gate voltage dependence of MOSFET noise variations. Under low gate overdrive, noise power variability as much as 12.2 dB is reported from a population of moderately sized FETs. However, the variability is reduced to 4.4 dB for the same population of devices at high gate overdrive. The relationship between inversion layer density within the vicinity of a trap and the trapped-charge-induced mobility fluctuation is investigated. The spatial gradient of the inversion layer profile is shown to impact the variability of noise. As the inversion layer becomes more uniform across the channel, noise variability is reduced. TCAD simulations and noise measurements are in agreement with the proposed theory. View full abstract»

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  • PMOSFET Reliability Study for Direct Silicon Bond (DSB) Hybrid Orientation Technology (HOT)

    Publication Year: 2007 , Page(s): 815 - 817
    Cited by:  Papers (1)
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (208 KB) |  | HTML iconHTML  

    The use of hybrid orientation technology with direct silicon bond wafers consisting of a (110) crystal orientation layer bonded to a bulk (100) handle wafer provides exciting opportunities for easier migration of bulk CMOS designs to higher performance materials, particularly (110) Si for PMOSFETs for higher hole mobility. In this letter, a 3times mobility improvement and 36% drive current gain were achieved for PMOSFETs on (110) substrates. A systematic investigation of PMOSFET reliability was conducted, and significant degradation of negative bias temperature instability lifetime on (110) orientation was observed due to higher density of dangling bonds. We also report the crystal orientation dependence on ultrathin nitrided gate oxide time-dependent dielectric breakdown. View full abstract»

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  • Measurement of Channel Stress Using Gate Direct Tunneling Current in Uniaxially Stressed nMOSFETs

    Publication Year: 2007 , Page(s): 818 - 820
    Cited by:  Papers (5)  |  Patents (1)
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (167 KB) |  | HTML iconHTML  

    We measure the conduction-band electron direct tunneling current through the 1.27-nm gate oxide of nMOSFETs transistors that undergo longitudinal stress via a layout technique. With known process parameters and published deformation potential constants as input, fitting of the measured direct tunneling current versus gate voltage leads to the channel stress of around 0, -100, and -300 MPa for a gate-to-trench isolation spacing of 2.4, 0.495, and 0.21 mum, respectively. To examine the accuracy of the method, a link with the mobility and threshold voltage measurements on the same device is conducted. The resulting piezoresistance coefficient and band offset are in good agreement with the literature values. The layout technique used is also validated. View full abstract»

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  • Valence Band Offset Measurements on Thin Silicon-on-Insulator MOSFETs

    Publication Year: 2007 , Page(s): 821 - 824
    Cited by:  Papers (2)
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (235 KB) |  | HTML iconHTML  

    The effect of quantum confinement in thin silicon-on-insulator double-gate MOSFETs has been directly determined from subthreshold current measurements for the first time. By comparing temperature-dependent subthreshold characteristics of p-type devices with different silicon layer thicknesses, the offset in the valence band edge induced by spatial carrier confinement in these very thin silicon layers was measured electrically. Changes in the band structure are important for future CMOS devices such as FinFETs. View full abstract»

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  • High Mobility Strained Ge pMOSFETs With High-κ/Metal Gate

    Publication Year: 2007 , Page(s): 825 - 827
    Cited by:  Papers (12)  |  Patents (3)
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (125 KB) |  | HTML iconHTML  

    Compressively strained Ge long channel ring-type pMOSFETs with high-kappa Si/SiO2/HfO2/TiN gate stacks are fabricated on Si0.2Ge0.8 virtual substrates. Effective oxide thickness is approximately 1.4 nm with low gate leakage current. A peak hole mobility of 640 cm2/ Vldrs and up to a four times enhancement over the Si/SiO2 universal curve are observed. Parasitic conduction within the Si-cap layers degrades the mobility at large vertical fields, although up to a 2.5 times enhancement over universal remains at a field of 0.9 MV/cm. View full abstract»

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  • Profiling of Nitride-Trap-Energy Distribution in SONOS Flash Memory by Using a Variable-Amplitude Low-Frequency Charge-Pumping Technique

    Publication Year: 2007 , Page(s): 828 - 830
    Cited by:  Papers (8)
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (139 KB) |  | HTML iconHTML  

    A variable-amplitude low-frequency charge-pumping technique is proposed to characterize the nitride-trap energy and spatial distributions in SONOS Flash memory cells. A numerical model based on Shockley-Read-Hall-like electron tunneling capture is used to correlate a charge-pumping current with the nitride-trap energy and position. By changing the frequency and pulse amplitude in charge-pumping measurement, a nitride-trap density, as a function of the trap position and energy, can be extracted. View full abstract»

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  • CMOS Dual-Work-Function Engineering by Using Implanted Ni-FUSI

    Publication Year: 2007 , Page(s): 831 - 833
    Cited by:  Papers (1)  |  Patents (2)
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (392 KB) |  | HTML iconHTML  

    For the first time, a simple CMOS fully silicided (FUSI) process achieving n/pMOS band-edge work function was demonstrated, which is fully compatible with conventional CMOS process. Dual-work-function CMOS FUSI, with a wide range of 800 mV, was achieved by implantation of Yb into the poly of the nMOS gate (4.1-eV work function) and Ga into the poly of the pMOS gate (4.9-eV work function), respectively. The placement of the tuning elements at the metal/dielectric interface was engineered with the thermal budget, as well as the implant dose and species. View full abstract»

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  • Substrate Bias Effect Linked to Parasitic Series Resistance in Multiple-Gate SOI MOSFETs

    Publication Year: 2007 , Page(s): 834 - 836
    Cited by:  Papers (9)
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (119 KB) |  | HTML iconHTML  

    It is generally recognized that very narrow silicon-on-insulator (SOI) fin field-effect transistors (FinFETs) are insensitive to substrate bias due to the strong electrostatic gate control. In this letter, we demonstrate, for the first time, that, in short-channel narrow FinFETs, substrate bias can dramatically change the on-current without change in the threshold voltage, subthreshold slope, and drain-induced barrier lowering, due to the modulation of the parasitic series resistance. Therefrom, contrary to general belief, very narrow short-channel multiple-gate field-effect transistors can be sensitive to substrate-related effects (buried oxide formation, irradiation, etc). Another important implication of the described effect is related to the diagnostics of the series resistance in SOI FinFETs and better prediction of their full intrinsic performance potential. View full abstract»

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  • A 0.26-μm2 U-Shaped Nitride-Based Programming Cell on Pure 90-nm CMOS Technology

    Publication Year: 2007 , Page(s): 837 - 839
    Cited by:  Papers (7)
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (313 KB) |  | HTML iconHTML  

    A novel one time programming (OTP) cell with a nitride-based storage has been developed for advanced programmable logic applications. This cell that is processed by pure logic process and decoupled with transistor gate oxide has a highly stable and extremely wide on/ off window. It exhibits a superior disturb immunity in program and read operations. In addition, a very small cell size (0.263 mum2 ) has been achieved using 90-nm pure CMOS logic process and is scalable in more advanced CMOS logic technologies by eliminating the constraint of transistor gate-oxide thickness. The all new OTP cell has a wide ON/OFF window and a superior writing efficiency by source-side injection programming mechanism. This novel OTP cell is a very promising programmable logic solution, with a fully CMOS-logic-compatible process below the 90-nm node. View full abstract»

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  • IEEE Electron Device Letters Information for authors

    Publication Year: 2007 , Page(s): 842
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  • Special issue on silicon carbide devices and technology

    Publication Year: 2007 , Page(s): 843 - 844
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  • Special issue on “Reliability of GaN, GaAs and related Compounds”

    Publication Year: 2007 , Page(s): 845
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    Freely Available from IEEE
  • Special Issue on Packaging Reliability

    Publication Year: 2007 , Page(s): 846
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IEEE Electron Device Letters publishes original and significant contributions relating to the theory, modeling, design, performance and reliability of electron devices.

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