IEEE Design & Test of Computers

Issue 4 • July-Aug. 2007

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Displaying Results 1 - 25 of 30
  • [Front cover]

    Publication Year: 2007, Page(s): c1
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  • IEEE Computer Society Membership Information

    Publication Year: 2007, Page(s): c2
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  • Call for Papers

    Publication Year: 2007, Page(s): 297
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  • Table of contents

    Publication Year: 2007, Page(s):298 - 299
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  • Design and CAD for Nanotechnologies

    Publication Year: 2007, Page(s): 300
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  • [Masthead]

    Publication Year: 2007, Page(s): 301
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  • Guest Editors' Introduction: The State of the Art in Nanoscale CAD

    Publication Year: 2007, Page(s):302 - 303
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  • An Overview of Nanoscale Devices and Circuits

    Publication Year: 2007, Page(s):304 - 311
    Cited by:  Papers (13)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (354 KB) | HTML iconHTML

    Conventional lithography-based vlsi technology (mostly using CMOS) has been extremely successful in the deep-submicron region. As CMOS approaches its fundamental physical limits (as evidenced by ultra thin gate oxides, short channel effects, and so on), researchers have begun investigating new technologies at extremely small feature sizes (such as nanoscale below 45 nm) for manufacturing future el... View full abstract»

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  • Tracking Uncertainty with Probabilistic Logic Circuit Testing

    Publication Year: 2007, Page(s):312 - 321
    Cited by:  Papers (10)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (960 KB) | HTML iconHTML

    The diverse nature of the faults and defects that may occur at nanoscale ranges necessitates new techniques for ATPG. This article proposes an efficient technique that relies on a probabilistic approach to detect and diagnose nontraditional faults and defects. View full abstract»

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  • Leakage Minimization Technique for Nanoscale CMOS VLSI

    Publication Year: 2007, Page(s):322 - 330
    Cited by:  Papers (16)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (909 KB) | HTML iconHTML

    Because of the continued scaling of technology and supply-threshold voltage, leakage power has become more significant in power dissipation of nanoscale CMOS circuits. Therefore, estimating the total leakage power is critical to designing low-power digital circuits. In nanometer CMOS circuits, the main leakage components are the subthreshold, gate-tunneling, and reverse-biased junction band-to-ban... View full abstract»

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  • Call for Papers

    Publication Year: 2007, Page(s): 331
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  • Practices in Mixed-Signal and RF IC Testing

    Publication Year: 2007, Page(s):332 - 339
    Cited by:  Papers (13)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (397 KB) | HTML iconHTML

    Mixed-signal (analog and digital) testing and RF testing pose major cost and quality challenges to the development of high-speed wired and wireless network and communication ICs. This article presents a brief overview of common industry practices for testing mixed-signal and RF ICs. We also present examples of DFT and BIST techniques for wired and wireless transceivers. Finally, we discuss the tes... View full abstract»

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  • Crosstalk- and SEU-Aware Networks on Chips

    Publication Year: 2007, Page(s):340 - 350
    Cited by:  Papers (24)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (878 KB) | HTML iconHTML

    On-chip routing elements are extensively used in complex NoC designs. Faulty operation of such elements due to crosstalk faults or soft errors can severely affect a device's functionality and performance. This article investigates the application of different hardware- and software-based approaches to improving these elements' dependability, and discusses the advantages and drawbacks of these appr... View full abstract»

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  • Call for Papers

    Publication Year: 2007, Page(s): 351
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  • ACID: Automatic Sort-Map Classification for Interactive Process Diagnosis

    Publication Year: 2007, Page(s):352 - 361
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (2245 KB) | HTML iconHTML

    Early detection of faulty process steps through process diagnosis is critical to the semiconductor industry. The AC-ID methodology can isolate the root causes of yield loss by combining end-of-line tests with process history information. The ACID software tool automates this methodology and is fully operational at several industry production sites. View full abstract»

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  • Empirical Validation of Yield Recovery Using Idle-Cycle Insertion

    Publication Year: 2007, Page(s):362 - 372
    Cited by:  Papers (3)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (1216 KB) | HTML iconHTML

    In this article, we evaluate the impact of idle-cycle insertion on yield by quantifying the number of test escapes. We empirically quantify false failures resulting from IR drop by inserting idle cycles at appropriate points during the scan test application protocol. Launch delay (LD) test delays the launch clock by inserting a certain amount of time (called idle cycles or idle time) after the las... View full abstract»

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  • Advertiser/Product Index

    Publication Year: 2007, Page(s): 373
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  • Variation-Tolerant, Power-Safe Pattern Generation

    Publication Year: 2007, Page(s):374 - 384
    Cited by:  Papers (6)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (866 KB) | HTML iconHTML

    By generating safe patterns - those that tolerate on-chip variations - this framework avoids false delay test failures. It uses power grid information and regional constraints on switching activity to minimize peak power and optimize the pattern set. Experimental results on benchmark circuits demonstrate the framework's effectiveness. View full abstract»

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  • IEEE Computer Society Information

    Publication Year: 2007, Page(s): 385
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  • Raisin: Redundancy Analysis Algorithm Simulation

    Publication Year: 2007, Page(s):386 - 396
    Cited by:  Papers (21)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (782 KB) | HTML iconHTML

    To increase redundancy repair efficiency and thus final yield in embedded- memory cores, we propose Raisin, a redundancy analysis algorithm simulation tool that can calculate an RA algorithm's repair rate, yield, associated memory configuration, and redundancy structure. Raisin lets users easily assess and plan redundant elements and subsequently develop BIRA algorithms and circuits, which are ess... View full abstract»

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  • IEEE Software 2007 Editorial Calendar

    Publication Year: 2007, Page(s): 397
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  • CEDA Currents

    Publication Year: 2007, Page(s):398 - 400
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  • IEEE Pervasive Computing 2007 Editorial Calendar

    Publication Year: 2007, Page(s): 401
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  • Book Review: An Assay of Biochips [review of two books: Design Automation Methods and Tools for Microfluidics-Based Biochips (Chakrabarty, K. and Zeng, J., eds.) and BioMEMS (Urban, G.A., ed.)

    Publication Year: 2007, Page(s):402 - 403
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  • DATC Newsletter

    Publication Year: 2007, Page(s):404 - 405
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Aims & Scope

This Periodical ceased production in 2012. The current retitled publication is IEEE Design & Test.

Full Aims & Scope

Meet Our Editors

Editor-in-Chief
Krishnendu Chakrabarty