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Electron Devices, IEEE Transactions on

Issue 8 • Date Aug. 2007

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Displaying Results 1 - 25 of 43
  • Table of contents

    Publication Year: 2007 , Page(s): C1 - 1810
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    Freely Available from IEEE
  • IEEE Transactions on Electron Devices publication information

    Publication Year: 2007 , Page(s): C2
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    Freely Available from IEEE
  • Simplified Surface Preparation for GaAs Passivation Using Atomic Layer-Deposited High- κ Dielectrics

    Publication Year: 2007 , Page(s): 1811 - 1817
    Cited by:  Papers (40)
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (510 KB) |  | HTML iconHTML  

    Atomic layer deposition (ALD) provides a unique opportunity to integrate high-quality gate dielectrics on III-V compound semiconductors. The physics and chemistry of a III-V compound semiconductor surface or interface are problems so complex that even after three decades research understanding is still limited. We report a simplified surface preparation process using ammonium hydroxide (NH4OH) to remove the native oxide and make the hydroxylated GaAs surface ready for ALD Al2O3 surface chemistry. The effectiveness of GaAs passivation with ALD is demonstrated with small hysteresis, 1%-2% frequency dispersion per decade at accumulation capacitance, and a mid-bandgap D it of 8 times1011 to 1times 1012 cm-2 ldr eV-1determined by the Terman method. The results from ammonium sulfide [(NH4)2S-,and hydrofluoric acid (HF)-, and hydrochloric acid (HCl)-treated surfaces and a surface with native oxide are also presented to compare with the results from the ammonium-hydroxide-treated surface. Fermi-level unpinning is also easily demonstrated on the ALD HfO2 and p-type GaAs interface. View full abstract»

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  • Dual-Gate E/E- and E/D-Mode AlGaAs/InGaAs pHEMTs for Microwave Circuit Applications

    Publication Year: 2007 , Page(s): 1818 - 1824
    Cited by:  Papers (5)
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (672 KB) |  | HTML iconHTML  

    In this paper, we developed dual-gate enhancement/enhancement-mode (E/E-mode) and enhancement/depletion-mode (E/D-mode) AlGaAs/InGaAs pHEMTs for high-voltage and high-power device applications. These dual-gate devices had a higher breakdown voltage (Vbr) and maximum oscillation frequency (fmax). This could be obtained because there were two depletion regions, and the total electrical field was shared between the two regions, leading to lower output conductance (go) and lower gate-to-drain capacitance (Cgd). The dual-gate device can be operated at a higher drain-to-source voltage (Vds), resulting in better linear gain and output power performance, as compared to a conventional single-gate E-mode GaAs pHEMT device. The maximum oscillation frequency obtained using the dual-gate E/E-mode device increased from 78 to 123 GHz. When operated at 2.4 GHz, the maximum RF output power of the single-gate E-mode and dual-gate E/D-mode devices increased from 636 to 810 mW/mm, respectively. We also produced a 2.4-GHz high-gain and high-power density two-stage power amplifier using dual-gate E/E and E/D-mode transistors. A linear gain of 40 dB and a maximum output power of 24 dBm were obtained. View full abstract»

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  • Suppression of Dynamic On-Resistance Increase and Gate Charge Measurements in High-Voltage GaN-HEMTs With Optimized Field-Plate Structure

    Publication Year: 2007 , Page(s): 1825 - 1830
    Cited by:  Papers (38)
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (320 KB) |  | HTML iconHTML  

    The dynamic on-resistance increase associated with the current collapse phenomena in high-voltage GaN high-electron-mobility transistors (HEMTs) has been suppressed by employing an optimized field-plate (FP) structure. The fabricated GaN-HEMTs of 600 V/4.7 A and 940 V/4.4 A for power-electronics applications employ a dual-FP structure consisting of a short-gate FP underneath a long-source FP. The measured on-resistance shows minimal increase during high-voltage switching due to increased electric-field uniformity between the gate and drain as a result of using the dual FP. The gate-drain charge Q gd for the fabricated devices has also been measured to provide a basis for discussion of the ability of high-speed switching operation. Although Q gd /A (A: active device area) was almost the same as that of the conventional Si-power MOSFETs, R on A was dramatically reduced to about a seventh of the reported 600-V Si-MOSFET value. Therefore, R on Q gd for 600-V device was reduced to 0.32 OmeganC, which was approximately a sixth of that for the Si-power MOSFETs. The high-voltage GaN-HEMTs have significant advantages over silicon-power MOSFETs in terms of both the reduced on-resistance and the high-speed switching capability. View full abstract»

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  • Electrical and Interfacial Characterization of Atomic Layer Deposited High- κ Gate Dielectrics on GaAs for Advanced CMOS Devices

    Publication Year: 2007 , Page(s): 1831 - 1837
    Cited by:  Papers (30)
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (271 KB) |  | HTML iconHTML  

    In this paper, electrical and interfacial properties of MOS capacitors with atomic layer deposited (ALD) Al2O3, HfO2, and HfAlO gate dielectrics on sulfur-passivated (S-passivated) GaAs substrates were investigated. HfAlO on p-type GaAs has shown superior electrical properties over Al2O3 or HfO2 on GaAs, and it is attributed to the reduction of the Ga-O formation at the interfacial layer. HfAlO on p-type GaAs exhibits the best electrical properties after postdeposition annealing (PDA) at 500degC. It is found that PDA, at above 500degC, causes a significant amount of Ga and As out-diffusion into the high-k dielectric, which degrades the interface, as well as bulk high-k properties. View full abstract»

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  • High-Resolution Raman Temperature Measurements in GaAs p-HEMT Multifinger Devices

    Publication Year: 2007 , Page(s): 1838 - 1842
    Cited by:  Papers (5)
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (550 KB) |  | HTML iconHTML  

    Self-heating in multifinger GaAs pseudomorphic-HEMT devices was investigated by micro-Raman spectroscopy. The device temperature was probed on the die as a function of applied bias, external heating, and device geometry. The temperature of the top GaAs layer was recorded inside the source-drain gap, as well as on the device periphery using 488-nm laser excitation. Obtained Raman temperatures were found to be higher than infrared thermography results, which is due to the improved spatial resolution of micro-Raman spectroscopy. Thermal resistance and crosstalk in the multifinger devices was evaluated as a function of thermal stress and finger pitch. View full abstract»

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  • Validity of the Parabolic Effective Mass Approximation in Silicon and Germanium n-MOSFETs With Different Crystal Orientations

    Publication Year: 2007 , Page(s): 1843 - 1851
    Cited by:  Papers (10)
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (379 KB) |  | HTML iconHTML  

    This paper investigates the validity of the parabolic effective mass approximation (EMA), which is almost universally used to describe the size and bias-induced quantization in n-MOSFETs. In particular, we compare the EMA results with a full-band quantization approach based on the linear combination of bulk bands (LCBB) and study the most relevant quantities for the modeling of the mobility and of the on-current of the devices, namely, the minima of the 2-D subbands, the transport masses, and the electron density of states. Our study deals with both silicon and germanium n-MOSFETs with different crystal orientations and shows that, in most cases, the validity of the EMA is quite satisfactory. The LCBB approach is then used to calculate the values of the effective masses that help improve the EMA accuracy. There are crystal orientations, however, where the 2-D energy dispersion obtained by the LCBB method exhibits features that are difficult to reproduce with the EMA model. View full abstract»

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  • Analysis of Wear-Out Degradation of a DFB Laser Using an Optical-Beam-Induced Current Monitor

    Publication Year: 2007 , Page(s): 1852 - 1859
    Cited by:  Papers (5)
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (480 KB) |  | HTML iconHTML  

    We investigated the degradation behavior of distributed feedback lasers by employing the optical-beam-induced current measurement technique. We showed that the degradation mechanism is governed by diffused defects at the waveguide other than those in the vicinity of the antireflection facet. In addition, we found that a diffused source is probably generated in the upper InP cladding layer above the grating during the growth of the upper InP cladding layer. View full abstract»

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  • Influence of Dislocation Loops on the Near-Infrared Light Emission From Silicon Diodes

    Publication Year: 2007 , Page(s): 1860 - 1866
    Cited by:  Papers (3)
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (421 KB) |  | HTML iconHTML  

    The infrared light emission of forward-biased silicon diodes is studied. Through ion implantation and anneal, dislocation loops were created near the diode junction. These loops suppress the light emission at the band-to-band peak around 1.1 mum. The so-called D1 line at 1.5 mum is strongly enhanced by these dislocation loops. We report a full study of photoluminescence and electroluminescence of these diodes. The results lead to new insights for the manufacturing approach of practical infrared light sources in integrated circuits. View full abstract»

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  • Improving Reliability of Copper Dual-Damascene Interconnects by Impurity Doping and Interface Strengthening

    Publication Year: 2007 , Page(s): 1867 - 1877
    Cited by:  Papers (10)  |  Patents (1)
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (1651 KB) |  | HTML iconHTML  

    Electromigration (EM)-derived void nucleation and growth in 65-nm-node dual-damascene interconnects were investigated, and the effects of impurity doping as well as copper adhesion strength to a capping-dielectric layer (CAP) are clarified. It is found that surface-reductive treatment of the copper line improves its adhesion to the SiCN-CAP, elongating the incubation time of voiding at the via bottom. An aluminum doping is effective in suppressing both the void nucleation and growth. Consequently, an aluminum-doped copper alloy with the strong copper/CAP interface improves the EM lifetime by 50 times compared to that of a conventional pure copper. These results clearly indicate that blocking migration paths of vacancies through both grain boundaries and the copper/CAP interface is essential in improving the EM reliability. View full abstract»

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  • A Broadband and Scalable Lumped Element Model for Fully Symmetric Inductors Under Single-Ended and Differentially Driven Operations

    Publication Year: 2007 , Page(s): 1878 - 1888
    Cited by:  Patents (2)
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (974 KB) |  | HTML iconHTML  

    A broadband and scalable 2-T model is developed to accurately simulate fully symmetric inductors with various dimensions. The 2-T model is defined to reflect the structure of an equivalent circuit with two identical T-model circuits. Two-step de-embedding is assisted by open and through pads for extraction of intrinsic characteristics. The accuracy is validated by 3-D full- wave electromagnetic simulation. A novel parameter extraction flow is established, and a single set of model parameters is derived to be valid for both single-ended and differentially driven topologies. The broadband accuracy is proven by a good match with S-parameters, L(omega), Re(Zln(omega)), and Q(omega) over frequencies up to 20 GHz. The scalability is justified by good fitting with either a linear or a parabolic function of spiral coil radii. Furthermore, all model parameters are frequency independent so as to ensure computation efficiency. This 2-T model consistently predicts the enhancement of Qmax by 20%-30% for the symmetric inductors under a differential excitation. The Q improvement is even better than 100% over broader frequencies beyond fm (Qmax). View full abstract»

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  • A Unified Model for Gate Capacitance–Voltage Characteristics and Extraction of Parameters of Si/SiGe Heterostructure pMOSFETs

    Publication Year: 2007 , Page(s): 1889 - 1896
    Cited by:  Papers (4)
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (199 KB) |  | HTML iconHTML  

    A unified model for gate capacitance-voltage characteristics of Si/SiGe heterostructure pMOSFETs is presented. This model is applicable to buried-channel, surface-channel, and dual-channel Si/SiGe heterostructure pMOSFETs. The results from the model are compared with the experimental results and are found to be in excellent agreement. A simple and accurate method for the extraction of parameters such as the valence band offset, Si cap layer thickness, threshold voltages, and substrate doping is also presented in this paper. View full abstract»

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  • Accuracy of Surface-Potential-Based Long–Wide-Channel Thick-Base MOS Transistor Models

    Publication Year: 2007 , Page(s): 1897 - 1909
    Cited by:  Papers (1)  |  Patents (1)
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (502 KB) |  | HTML iconHTML  

    This paper answers the frequently asked question, ldquoHow accurate are the approximate long-wide-channel thick-base MOS transistor baseline models that have been used to develop the compact models for computer-aided circuit designs?rdquo Three commonly used surface-potential-based(Us = qPsis / kT ) approximations of the ionized impurity bulk charge are evaluated as follows: Q B alpha (i) (Us)1/2; (ii) (Us -1)1/2; (iii)[Us -1 + exp(-U s )]1/2. The double-integral baseline model for comparison includes the self-consistent remote charge-neutrality boundary condition, minority carriers, and space-constant impurity-concentration and oxide thickness. Percentage deviations of the approximations from the baseline model are computed for the dc drain current. Approximation (i) show a significant deviation, which is ~ 16% at threshold voltage, diverging rapidly in the subthreshold range toward flatband. Approximations (ii) and (iii) show a few percent (1% to 2%) deviations in both inversion and subthreshold ranges but diverge widely below subthreshold and in accummulation. A new analytical model is tested and shows better than 10% accuracy below subthreshold and in accummulation. View full abstract»

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  • P-Type Floating Gate for Retention and P/E Window Improvement of Flash Memory Devices

    Publication Year: 2007 , Page(s): 1910 - 1917
    Cited by:  Papers (6)  |  Patents (1)
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (646 KB) |  | HTML iconHTML  

    A flash memory with a lightly doped p-type floating gate is proposed, which improves charge retention and programming/erase (P/E) Vth window. Improvement in P/E window is enhanced for cells with smaller capacitance coupling ratio, which is important for future scaled flash memory cells. Both device simulation and experimental verification are presented. View full abstract»

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  • Discrete Dopant Effects on Statistical Variation of Random Telegraph Signal Magnitude

    Publication Year: 2007 , Page(s): 1918 - 1925
    Cited by:  Papers (39)
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (413 KB) |  | HTML iconHTML  

    This paper discusses the discrete channel dopant effects on the statistical variation of random telegraph signal (RTS) magnitude, which is defined by the threshold-voltage shift by RTS in MOSFETs. An analytical model for the statistical variation of RTS magnitude is presented. Considering discrete dopant effects, the RTS magnitude of MOSFETs exhibits a log-normal distribution, while the threshold voltage itself exhibits a normal distribution. The threshold-voltage shift by RTS will become a serious concern in 50-nm Flash memories and beyond. View full abstract»

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  • Design of Highly Efficient Light-Trapping Structures for Thin-Film Crystalline Silicon Solar Cells

    Publication Year: 2007 , Page(s): 1926 - 1933
    Cited by:  Papers (47)  |  Patents (3)
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (784 KB) |  | HTML iconHTML  

    We present a design optimization of a highly efficient light-trapping structure to significantly increase the efficiency of thin-film crystalline silicon solar cells. The structure consists of an antireflection (AR) coating, a silicon active layer, and a back reflector that combines a diffractive reflection grating with a distributed Bragg reflector. We have demonstrated that with careful design optimization, the presented light-trapping structure can lead to a remarkable cell-efficiency enhancement for the cells with very thin silicon active layers (typically 2.0-10.0 mum) due to the significantly enhanced absorption in the wavelength range of 800-1100 nm. On the other hand, less enhancement has been predicted for much thicker cells (i.e.,>100 mum) due to the limited absorption increase in this wavelength range. According to our simulation, the overall cell efficiency can be doubled for a 2.0-mum-thick cell with light-trapping structure. It is found that the improvement is mainly contributed by the optimized AR coating and diffraction grating with the corresponding relative improvements of 36% and 54%, respectively. The simulation results show that the absolute cell efficiency of a 2.0-mum-thick cell with the optimal light-trapping structure can be as large as 12%. View full abstract»

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  • Design Optimization and Performance Projections of Double-Gate FinFETs With Gate–Source/Drain Underlap for SRAM Application

    Publication Year: 2007 , Page(s): 1934 - 1942
    Cited by:  Papers (15)
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (787 KB) |  | HTML iconHTML  

    Physical device/circuit simulations are used to explore 6T-SRAM cell design and scaling using double-gate (DG) FinFETs with optimized gate-source/drain (G-S/D) underlap. The underlap is designed for the control of threshold voltage (Vt) in the nanoscale FinFET with undoped ultrathin body (UTB). DG FinFETs with underlap are first characterized in terms of for various S/D-extension lengths (Lext), lateral doping-density straggles (sigmaL), and fin-UTB thicknesses (wSi). The relation between and read-static noise margin (SNM) is established to define an optimal SRAM cell, for the Semiconductor Industry Association's International Technology Roadmap for Semiconductors (ITRS) HP45 node with Lg=18 nm, with large SNM as well as large write-0 margin and good immunity to process-induced variations of Lext, sigmaL, wSi, and Lg. Then, a scalability study of the DG FinFET-based SRAM cell is done, showing a continual significant benefit of the optimally designed doable underlaps to the end of the ITRS. In addition to the SRAM application, the novel idea of FinFET Vt control via underlap design is stressed, and its application to high-performance CMOS is discussed. View full abstract»

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  • Semi-Analytical Modeling of Short-Channel Effects in Si and Ge Symmetrical Double-Gate MOSFETs

    Publication Year: 2007 , Page(s): 1943 - 1952
    Cited by:  Papers (29)  |  Patents (1)
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (298 KB) |  | HTML iconHTML  

    A simple analytical expression of the 2-D potential distribution along the channel of silicon symmetrical double-gate (DG) MOSFETs in weak inversion is derived. The analytical solution of the potential distribution is compared with the numerical solution of the 2-D Poisson's equation in terms of the channel length L, the silicon thickness t Si, and the gate oxide thickness t OX. The obtained results show that the analytical solution describes, with good accuracy, the potential distribution along the channel at different positions from the gate interfaces for well-designed devices when the ratio of L/t Si is ges 2-3. Based on the 2-D extra potential induced in the silicon film due to short-channel effects (SCEs), a semi-analytical expression for the subthreshold drain current of short-channel devices is derived. From the obtained subthreshold characteristics, the extracted device parameters of the subthreshold slope, drain-induced barrier lowering, and threshold voltage are discussed. Application of the proposed model to devices with silicon replaced by germanium demonstrates that the germanium DG MOSFETs are more prone to SCEs. View full abstract»

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  • Explanation of SILC Probability Density Distributions With Nonuniform Generation of Traps in the Tunnel Oxide of Flash Memory Arrays

    Publication Year: 2007 , Page(s): 1953 - 1962
    Cited by:  Papers (4)
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (333 KB) |  | HTML iconHTML  

    In this paper, we develop a detailed physical model to interpret the dependence of the stress induced leakage current (SILC) distributions on the nature and position of the generated defects, and we exploit it to reconsider in detail previously published experimental data on the statistical distribution of the SILC in Flash arrays. We found that a unique symmetrical spatial distribution of traps, which is rapidly decreasing from the Si-SiO2 interfaces toward the center of the oxide, can explain the oxide-thickness and stress-level dependence of the measured SILC distributions. The generation of cooperating defects with increasing stress time is also analyzed and discussed. View full abstract»

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  • SPICE Models of Fluorine-Ion-Irradiated CMOS Devices

    Publication Year: 2007 , Page(s): 1963 - 1971
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (500 KB) |  | HTML iconHTML  

    CMOS image sensors are attractive for space applications due to their low-power and system-on-chip features. The typical active pixel sensor (APS) is composed of a photodiode and several transistors. Using Fluorine +7 ions with an energy of 17 MeV, the effects of radiation are investigated on photodiodes and transistors manufactured using a standard 0.35-mum CMOS process. Simulation results show that the range of these ions overlaps with the active region of the device. Thus, the proximity effect of the ions on the performance of the device can be important. The tested photodiode showed a leakage current increase after it was irradiated with fluorine ions. The ideality factor of recombination current is observed to increase up to 4. Moreover, an increase in leakage current and absolute threshold voltage was observed in fluorine-ion-irradiated nMOS and pMOS transistors. In this paper, behavioral SPICE models are developed to analyze the contribution of these components to an overall increase in dark current of a CMOS APS. View full abstract»

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  • The Role of Nitrogen on Charge-Trapping-Induced Vth Instability in HfAlON High-κ Gate Dielectric With Metal and Poly-Si Gate Electrodes

    Publication Year: 2007 , Page(s): 1972 - 1977
    Cited by:  Papers (1)  |  Patents (2)
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (233 KB) |  | HTML iconHTML  

    The impact of N on HfAlON dielectrics has been extensively studied in devices with TaN metal and poly-Si gate electrodes. A similar trend of the N effects was observed in both TaN and poly-Si devices in terms of equivalent oxide thickness, gate leakage current, threshold voltage (V th), transconductance, and subthreshold swing. However, compared to the HfAlON with TaN metal gate, a severe V th instability induced by charge trapping was generally observed in the poly-Si/HfAlON devices. In addition, the incorporation of N in the HfAlON films was found to play an opposite role in the V th instability between the TaN and poly-Si devices: In the TaN metal gate devices, the charge-trapping-induced V th instability in the HfAlON was slightly degraded by increasing the N concentration, whereas the V th instability was remarkably improved by increasing the N concentration in the poly-Si gate devices. The degradation of the V th instability observed in the TaN metal gate devices is believed to be due to the increase in preexisting bulk traps that is caused by incorporating N into the gate dielectric. The significant improvement on the V th instability in the devices with poly-Si gate could be mainly attributed to the remarkable suppression of electron trapping at oxygen vacancies by adding N into the high-K gate dielectric. View full abstract»

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  • The Localized-SOI MOSFET as a Candidate for Analog/RF Applications

    Publication Year: 2007 , Page(s): 1978 - 1984
    Cited by:  Papers (7)
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (400 KB) |  | HTML iconHTML  

    In this paper, the characteristics of a localized-SOI (L-SOI) MOSFET are investigated for analog/RF applications. In the L-SOI device, the source/drain regions are quasi-surrounded by L-type oxide layers to reduce junction capacitance and avoid source/drain punchthrough, while the channel is directly connected with the substrate to alleviate the self-heating effect. Such structures can combine the advantages of both bulk and SOI MOSFETs and avoid their issues. Due to the unique structure of this novel device, the L-SOI MOSFET can exhibit excellent analog/RF behaviors. Higher g m / I ds ratio and intrinsic gain (g m / g ds)can be received compared with the conventional SOI structure, particularly at low gate bias. Higher and , which are due to higher g m and reduced gate capacitance, can be observed in the L-SOI MOSFET. In addition, better noise performance can be achieved resulting from reduced lattice temperature and improved g m . Thus, the L-SOI MOSFET can be considered as one of the potential candidates for analog/RF applications. View full abstract»

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  • Maximum Active Concentration of Ion-Implanted Phosphorus During Solid-Phase Epitaxial Recrystallization

    Publication Year: 2007 , Page(s): 1985 - 1993
    Cited by:  Papers (1)
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (337 KB) |  | HTML iconHTML  

    In this paper, we showed that the maximum active P concentration of approximately 2 times1020 cm-3 exists during solid-phase epitaxial recrystallization (SPER). This maximum active concentration is close to the reported values for other active impurity concentrations during SPER. We introduced the concept of an isolated impurity that has no neighbor impurities with a certain lattice range. Assuming that impurities interact with three or four neighbor impurities, we can explain the activation phenomenon during SPER. According to our model, the isolated P concentration N iso has a maximum value of approximately 2 times1020 cm-3 at a total impurity concentration of approximately 1021 cm-3, and it decreases with a further increase in total impurity concentration. Deactivation occurs after the completion of SPER with increasing annealing time, and the active impurity concentration decreases with time but is always higher than the maximum diffusion concentration N Diff max. We also observed that N Diff max is independent of the annealing time despite nonthermal activation in the high-concentration region. We evaluated the dependence of N Diff max on annealing temperatures. We think that this N Diff max can be regarded as the electrical solid solubility N Esol that the active impurity concentration reaches in thermal equilibrium. We observed the transient enhanced diffusion (TED) after the completion of SPER, and that, the deactivation process continues during and after TED, and the corresponding diffusion coefficient is still much higher than that in thermal equilibrium even after TED has finished, which suggests that the deactivation process releases point defects. View full abstract»

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  • Noise Modeling in Lateral Nonuniform MOSFET

    Publication Year: 2007 , Page(s): 1994 - 2001
    Cited by:  Papers (5)
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (224 KB) |  | HTML iconHTML  

    In this paper, we present an analytical noise modeling methodology for lateral nonuniform MOSFET. We demonstrate that the noise properties of lateral nonuniform MOSFETs are considerably different from the prediction obtained with the conventional Klaassen-Prins (KP)-based methods which, at low gate voltages, depending on the doping profile can overestimate the thermal noise by 2-3 orders of magnitude. We show that the presence of lateral nonuniformity makes the vector impedance field (the quantity responsible for noise propagation) position and bias dependent. This insight clearly explains the observed discrepancy and shows that the bias dependence of the important noise parameters cannot be predicted by conventional KP-based methods. View full abstract»

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Aims & Scope

IEEE Transactions on Electron Devices publishes original and significant contributions relating to the theory, modeling, design, performance and reliability of electron and ion integrated circuit devices and interconnects.

 

Full Aims & Scope

Meet Our Editors

Acting Editor-in-Chief

Dr. Paul K.-L. Yu

Dept. ECE
University of California San Diego