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Network, IEEE

Issue 4 • Date July-August 2007

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Displaying Results 1 - 12 of 12
  • Front cover - IEEE Network - Front cover

    Page(s): c1
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    Freely Available from IEEE
  • Table of contents

    Page(s): 1
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    Freely Available from IEEE
  • On Voyeuristic Protocols [Editor's Note]

    Page(s): 2 - 3
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (193 KB) |  | HTML iconHTML  

    First Page of the Article
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  • Network Systems Architecture [Guest Editorial]

    Page(s): 6 - 7
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    The seven articles in this special issue focus on network systems architecture. They cover several aspects of the architectures of network systems, including specific subsystems (components), distributed solutions, and service level architectures. View full abstract»

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  • New books and multimedia

    Page(s): 4 - 5
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    Freely Available from IEEE
  • Converging the Evolution of Router Architectures and IP Networks

    Page(s): 8 - 14
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (104 KB) |  | HTML iconHTML  

    Although IP is widely recognized as the platform for next-generation converged networks, unfortunately, it is heavily burdened by its heritage of almost 30 years. Nowadays, network operators must devote significant resources to perform essential tasks, such as traffic engineering, policy enforcement, and security. In this article, we argue that one of the principal reasons for this is the way control and forwarding planes are interspersed in IP networks today. We review the architectural developments that led to the current situation, and we reason that centralization of network control functionality can constitute a solution to the pressing problems of the contemporary Internet. View full abstract»

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  • Multistage Switching Architectures for Software Routers

    Page(s): 15 - 21
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (145 KB) |  | HTML iconHTML  

    Software routers based on personal computer (PC) architectures are becoming an important alternative to proprietary and expensive network devices. However, software routers suffer from many limitations of the PC architecture, including, among others, limited bus and central processing unit (CPU) bandwidth, high memory access latency, limited scalability in terms of number of network interface cards, and lack of resilience mechanisms. Multistage PC-based architectures can be an interesting alternative since they permit us to i) increase the performance of single- software routers, ii) scale router size, iii) distribute packet-manipulation and control functionality, iv) recover from single-component failures, and v) incrementally upgrade router performance. We propose a specific multistage architecture, exploiting PC-based routers as switching elements, to build a high-speed, large-size, scalable, and reliable software router. A small-scale prototype of the multistage router is currently up and running in our labs, and performance evaluation is under way. View full abstract»

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  • Parallel Programmable Ethernet Controllers: Performance and Security

    Page(s): 22 - 28
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (112 KB) |  | HTML iconHTML  

    Programmable network interfaces can provide network servers with a flexible interface to high-bandwidth Ethernet links, but they face critical software and architectural challenges. This article explores architectural and software support for an efficient programmable 10 Gigabit Ethernet controller. The design is then extended to support a self-securing Gigabit Ethernet controller that performs intrusion detection on all network data frames. Both raw performance and security require high- bitrate frame data transfer, low-latency metadata access, and intensive computational capacity while still operating under the area, cost, and power budget of a peripheral device. These goals are achieved using a combination of parallel lightweight processing cores, an explicitly-partitioned memory system, and dedicated hardware assists. The firmware on the network interface is designed to utilize these resources efficiently by exploiting frame-level, flow-level, and task-level concurrency. View full abstract»

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  • Runtime Support for Multicore Packet Processing Systems

    Page(s): 29 - 37
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (150 KB) |  | HTML iconHTML  

    Network processors promise a flexible, programmable packet processing infrastructure for network systems. To make full use of the capabilities of network processors, it is imperative to provide the ability to dynamically adapt to changing traffic patterns in the form of a network processor runtime system. The differences from existing operating systems and the main challenges lie in the multiprocessor nature of NPs, their on-chip resource constraints, and real-time processing requirements. In this article we explore the key design trade-offs that need to be considered when designing a network processor operating system. In particular, we explore the performance impact of application analysis on partitioning, traffic characterization, workload mapping, and runtime adaptation. We present and discuss qualitative and quantitative results in the context of a particular application analysis and mapping framework. The observations and conclusions are generally applicable to any runtime environment for network processors. View full abstract»

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  • Path-Computation-Element-Based Architecture for Interdomain MPLS/GMPLS Traffic Engineering: Overview and Performance

    Page(s): 38 - 45
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (151 KB) |  | HTML iconHTML  

    The Path Computation Element Working Group at the Internet Engineering Task Force is chartered to specify a PCE-based architecture for the path computation of interdomain MPLS- and GMPLS-based traffic engineered label switched paths. In this architecture, path computation does not occur at the head-end LSR, but on another path computation entity that may not be physically located on the head-end LSR. This method is greatly different from the traditional "per-domain" approach to path computation. This article presents analysis and results that compare performance of the PCE architecture with the current state-of-the-art approach. Detailed simulations are undertaken on varied and realistic scenarios where preliminary results show several performance benefits from the deployment of PCE. To provide a complete overview of significant development taking place in this area, milestones and progress at the IETF PCE WG are also discussed. View full abstract»

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  • Analysis of Shared Memory Priority Queues with Two Discard Levels

    Page(s): 46 - 50
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (124 KB) |  | HTML iconHTML  

    Two-rate SLAs become increasingly popular in today's Internet, allowing a customer to save money by paying one price for committed traffic and a much lower price for additional traffic that is not guaranteed. These types of SLAs are suggested for all types of traffic from best effort to QoS constrained applications. In access networks, where these SLAs are prevalent, shared memory switches are a common feature of architecture. Thus, dimensioning and management of shared memory queues for multiple priorities, each with two levels of guarantees, becomes an interesting challenge. We present a simple analysis of a multipriority multi-discard-level system controlled by a buffer occupancy threshold policy aimed at assuring SLA compliance for conforming (i.e., committed) traffic, and performance maximization for nonconforming (i.e., excess) traffic. Our analysis shows how to calculate the different system parameters: total buffer size, threshold position, and offered load control performance for the committed and excess traffic. Our suggested design enables assuring high SLA compliance for conforming traffic and performance maximization for nonconforming traffic. View full abstract»

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  • Improving Satellite Multicast Security Scalability by Reducing Rekeying Requirements

    Page(s): 51 - 56
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (236 KB) |  | HTML iconHTML  

    As multicasting technologies grow in popularity, so does the need for scalable security architectures to support the user base. Significant research efforts are ongoing in the areas of group-key distribution and management. However, little research has addressed the security of very large, distributed groups communicating via low-earth orbit satellite networks. In this article, we review the requirements common to most secure, multicast networking environments; discuss existing scalable multicast security architectures; and present a novel modular scalable architecture for secure multicast, adapted to a low-earth orbit satellite system. Simulated results reveal a twelve-fold reduction in average user rekeying and an order of magnitude reduction in required key distribution versus the baseline architecture. View full abstract»

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Aims & Scope

IEEE Network covers topics which include: network protocols and architecture; protocol design and validation; communications software; network control, signaling and management; network implementation (LAN, MAN, WAN); and micro-to-host communications.

Full Aims & Scope

Meet Our Editors

Editor-in-Chief
Xuemin (Sherman) Shen, PhD
Engineering University of Waterloo