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IEEE Transactions on Computers

Issue 10 • Date Oct 1992

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Displaying Results 1 - 16 of 16
  • On-line scheduling of real-time tasks

    Publication Year: 1992, Page(s):1326 - 1331
    Cited by:  Papers (33)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (604 KB)

    An optimal on-line scheduler is given for a set of real-time tasks with one common deadline on m processors. It is shown that no optimal scheduler can exist for tasks with two distinct deadlines. Finally, an optimal on-line scheduler is given for situations where processors can go down unexpectedly View full abstract»

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  • Adaptation of the Mactaggart and Jack complex multiplication algorithm for floating-point operators

    Publication Year: 1992, Page(s):1324 - 1326
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (264 KB)

    With a suitable treatment of the exponents in the input operands, a hardware implementation of the Mactaggart and Jack fixed-point complex multiplication algorithm can also calculate a floating-point product with no loss in accuracy from the greater dynamic range of the floating-point inputs. This floating-point technique can be extended to any sum to two products operation, such as encountered in... View full abstract»

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  • New techniques for constructing EC/AUED codes

    Publication Year: 1992, Page(s):1318 - 1324
    Cited by:  Papers (18)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (468 KB)

    Two new techniques for constructing t-EC/AUED (error correcting/all unidirectional error detection) codes are presented. The first technique modifies the t-EC/AUED code in such a way that the weight distribution of the original code is reduced. So, a smaller tail is needed. Frequently, this technique gives less overall redundancy than the best available t-EC/AUED codes. ... View full abstract»

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  • Traffic routing for multicomputer networks with virtual cut-through capability

    Publication Year: 1992, Page(s):1257 - 1270
    Cited by:  Papers (15)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (948 KB)

    The problem of selecting routes for interprocess communication in a network with virtual cut-through capability while balancing the network load and minimizing the number of times that a message gets buffered is addressed. The approach taken is to formulate the route selection problem as a minimization problem, with a link cost function that depends upon the traffic through the link. The form of t... View full abstract»

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  • Bit-parallel arithmetic in a massively-parallel associative processor

    Publication Year: 1992, Page(s):1201 - 1210
    Cited by:  Papers (14)  |  Patents (25)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (784 KB)

    A simple but powerful architecture based on the classical associative processor model is proposed. By distributing logic among slices of storage cells such that a number of bit-planes share a simple logic unit, bit-parallel arithmetic for massively parallel processing becomes feasible. For m-bit operands, this architecture enables complex operations such as multiplication and division to ... View full abstract»

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  • Vector register allocation

    Publication Year: 1992, Page(s):1290 - 1317
    Cited by:  Papers (14)  |  Patents (5)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (2308 KB)

    The problem of allocating vector registers on supercomputers is addressed in the context of compiling vector languages. Two subproblems must be solved to achieve good vector register allocation. First, the vector operations in the source program must be subdivided into sections that fit the hardware of the target machine. Second, the locality of reference of the vector operations must be improved ... View full abstract»

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  • A fault-tolerant communication scheme for hypercube computers

    Publication Year: 1992, Page(s):1242 - 1256
    Cited by:  Papers (103)  |  Patents (2)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (1176 KB)

    A fault-tolerant communication scheme that facilitates near-optimal routing and broadcasting in hypercube computers subject to node failures is described. The concept of an unsafe node is introduced to identify fault-free nodes that may cause communication difficulties. It is shown that by only using `feasible' paths that try to avoid unsafe nodes, routing and broadcasting can be substantially sim... View full abstract»

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  • Single-precision multiplier with reduced circuit complexity for signal processing applications

    Publication Year: 1992, Page(s):1333 - 1336
    Cited by:  Papers (61)  |  Patents (1)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (300 KB)

    When two numbers are multiplied, a double-wordlength product is produced. In applications where only the single-precision product is required, the double-wordlength result is rounded to single-precision. Hence, in single-precision applications, it is not necessary to compute the least significant part of the product exactly. Instead, it is only necessary to estimate the carries generated in the co... View full abstract»

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  • Computer benchmark evaluation and design of experiments: a case study

    Publication Year: 1992, Page(s):1279 - 1289
    Cited by:  Papers (4)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (968 KB)

    The author defines installation tuning and promotes it as an important area of concern for computer configurations. Examples include deciding on the paging configuration for a particular workload and partitioning available memory into system and user areas. Available tuning options are often difficult to select due to poor understanding of their effects, so analytic models rarely exist for these a... View full abstract»

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  • Wavelength division multiple access channel hypercube processor interconnection

    Publication Year: 1992, Page(s):1223 - 1241
    Cited by:  Papers (56)  |  Patents (2)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (1476 KB)

    A hypercube-based structure in which optical multiple access channels span the dimensional axes is introduced. This severely reduces the required degree, since only one I/O port is required per dimension. However, good performance is maintained through the high-capacity characteristics of optical communication. The reduction in degree is shown to have significant system complexity implications. Fo... View full abstract»

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  • Detection and location of multiple faults in baseline interconnection networks

    Publication Year: 1992, Page(s):1340 - 1344
    Cited by:  Papers (7)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (436 KB)

    An algorithm for fault diagnosis (detection and location) of baseline interconnection networks in the presence of multiple faults is presented. This algorithm requires 2(1+log2 N) tests, where log2 N is the number of stages. Multiple fault diagnosis is possible provided: (a) there exists no logically erroneous and unidentified outputs in each faulty switchin... View full abstract»

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  • Decomposition of complex multipliers using polynomial encoding

    Publication Year: 1992, Page(s):1331 - 1333
    Cited by:  Papers (2)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (232 KB)

    A method for complex multiplication that relies on encoding 2n -bit complex numbers as polynomials of degree 7 in the ring of polynomials modulo x8-1 with n/4-bit coefficients is introduced. Complex multiplication can then be performed with an 8-point cyclic convolution plus some conversion overhead and, with care, this can be done without introducing any erro... View full abstract»

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  • Comparison of hybrid minimum laxity/first-in-first-out scheduling policies for real-time multiprocessors

    Publication Year: 1992, Page(s):1271 - 1278
    Cited by:  Papers (8)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (756 KB)

    The behavior of two policies for scheduling customers with deadlines until the beginning of service onto multiprocessors is studied. Both policies attempt to approximate the performance of the minimum laxity (ML) scheduling policy without incurring its complete overhead by dividing the queue in two: one, of maximum size n>0, managed using the minimum laxity policy, and another, of unbo... View full abstract»

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  • Processor architecture and data buffering

    Publication Year: 1992, Page(s):1211 - 1222
    Cited by:  Papers (2)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (1096 KB)

    The tradeoff between visualizing or hiding the highest levels of the memory hierarchy, which impacts both performance and scalability, is examined by comparing a set of architectures from three major architecture families: stack, register, and memory-to-memory. The stack architecture is used as reference. It is shown that scalable architectures require at least 32 words of local memory and therefo... View full abstract»

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  • Cayley graphs with optimal fault tolerance

    Publication Year: 1992, Page(s):1337 - 1339
    Cited by:  Papers (12)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (332 KB)

    If H is a quasiminimal generating set for a finite group G, it is proved that the Cayley graph (G; H) has optimal fault tolerance unless it belongs to a special family View full abstract»

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  • Self synchronized asynchronous sequential pass transistor circuits

    Publication Year: 1992, Page(s):1344 - 1348
    Cited by:  Papers (4)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (404 KB)

    A new class of CMOS VLSI asynchronous sequential circuits utilizing pass transistors is introduced. This class of self synchronizing circuits eliminates the need for critical race free state assignments. These circuits synchronize the transition path action by forcing the circuit to sequence through proper unstable states View full abstract»

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The IEEE Transactions on Computers is a monthly publication with a wide distribution to researchers, developers, technical managers, and educators in the computer field.

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Meet Our Editors

Editor-in-Chief
Paolo Montuschi
Politecnico di Torino
Dipartimento di Automatica e Informatica
Corso Duca degli Abruzzi 24 
10129 Torino - Italy
e-mail: pmo@computer.org