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Circuits and Systems II: Express Briefs, IEEE Transactions on

Issue 7 • Date July 2007

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Displaying Results 1 - 23 of 23
  • Table of contents

    Page(s): C1 - C4
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  • IEEE Transactions on Circuits and Systems—II: Express Briefs publication information

    Page(s): C2
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  • A Fast-Lock Wide-Range Delay-Locked Loop Using Frequency-Range Selector for Multiphase Clock Generator

    Page(s): 561 - 565
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (1502 KB) |  | HTML iconHTML  

    This brief describes a fast-lock mixed-mode delay-locked loop (DLL) for wide-range operation and multiphase outputs. The architecture of the proposed DLL uses the mixed-mode time-to-digital-converter scheme for a frequency-range selector and a coarse tune circuit to reduce the lock time. A multi-controlled delay cell for the voltage-controlled delay line is applied to provide the wide operating frequency range and low-jitter performance. The charge pump circuit is implemented using a digital control scheme to achieve adaptive bandwidth. The chip is fabricated in a 0.25-mum standard CMOS process with a 2.5-V power-supply voltage. The measurements show that this DLL can be operated correctly when the input clock frequency is changed from 32 to 320 MHz, and can generate ten-phase clocks within a single cycle without the false locking problem associated with conventional DLLs and wide-range operation. At 200 MHz, the measured rms random jitter and peak-to-peak deterministic jitter are 4.44 and 15 ps, respectively. Moreover, the lock time is less than 22 clock cycles. This DLL occupies less area (0.07 mm2) and dissipates less power (15 mW) than other wide-range DLLs. View full abstract»

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  • A 62.5–625-MHz Anti-Reset All-Digital Delay-Locked Loop

    Page(s): 566 - 570
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (862 KB) |  | HTML iconHTML  

    An anti-reset all-digital delay-locked loop (DLL) is presented. When the input clock frequency changes significantly, the dynamic frequency detector re-locks the DLL without any external reset signal. The proposed binary time-to-digital converter (BTDC) reduces effectively the hardware, compared with a conventional TDC. Unlike many previous all-digital DLLs, this one is a closed feedback loop that can track environmental variations. The input frequency range can be operated from 62.5-625 MHz. It spends at most six cycles to synchronize the input and output clocks. View full abstract»

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  • Low-Power Tunable Analog Circuit Blocks Based on Nanoscale Double-Gate MOSFETs

    Page(s): 571 - 575
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (790 KB) |  | HTML iconHTML  

    We illustrate unique examples of low-power tunable analog circuits built using independently driven nanoscale DG-MOSFETs, where the top gate response is altered by application of a control voltage on the bottom gate. In particular, we provide examples for a single-ended CMOS amplifier pair, a Schmitt trigger circuit and a operational transconductance amplifier C filter, circuit blocks essential for low-noise high-performance integrated circuits for analog and mixed-signal applications. The topologies and biasing schemes explored here show how the nanoscale DG-MOSFETs may be used for efficient, tolerant and smaller circuits with tunable characteristics. View full abstract»

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  • A Frequency-Translating Hybrid Architecture for Wide-Band Analog-to-Digital Converters

    Page(s): 576 - 580
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (202 KB) |  | HTML iconHTML  

    A parallel architecture for high-bandwidth analog-to-digital conversion is presented. The proposed architecture uses frequency translation along with multi-rate signal processing to digitize a wide-band continuous-time analog signal through an array of identical narrowband analog-to-digital converters (ADCs). The basic idea behind this structure is to decompose the input signal into smaller frequency (channels). Each channel is composed of a two-path system that includes mixers, identical low-pass filters and identical baseband ADCs. The signal in each two-path channel is sampled and digitized into narrowband quadrature signals. After digitizing the signal in each channel, the low-rate subband samples are upconverted back to their respective center frequencies, then filtered and combined to reconstruct the digital representation of the original wide-band input signal. The digital filters are designed to minimize the reconstruction error. The effects of some major nonidealities are discussed. Several simulation results are also presented to demonstrate the performance of the system. View full abstract»

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  • Single Transistor High-Impedance Tail Current Source With Extended Common-Mode Input Range and Reduced Supply Requirements

    Page(s): 581 - 585
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (1133 KB) |  | HTML iconHTML  

    A compact implementation of a single transistor tail current source with very high output impedance (>40 MOmega) and low-voltage requirements is introduced. The tail transistor can operate with less than a drain-source saturation voltage and allows implementation of low-voltage differential pairs with wide common-mode input range and very high common-mode rejection ratio. Simulation and experimental results are shown that validate the proposed circuit. View full abstract»

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  • A Multi-Mode Power Gating Structure for Low-Voltage Deep-Submicron CMOS ICs

    Page(s): 586 - 590
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (696 KB) |  | HTML iconHTML  

    Most existing power gating structures provide only one power-saving mode. We propose a novel power gating structure that supports both a cutoff mode and an intermediate power-saving and data-retaining mode. Experiments with test structures fabricated in 0.13-mum CMOS bulk technology show that our power gating structure yields an expanded design space with more power-performance tradeoff alternatives. View full abstract»

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  • A mux-based High-Performance Single-Cycle CMOS Comparator

    Page(s): 591 - 595
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (877 KB) |  | HTML iconHTML  

    In this brief, a new architecture for high-fan-in CMOS comparator is proposed. The architecture is based on a hierarchical two-stage comparator structure and a dynamic MUX is used instead of a comparator in the second stage of the structure. By doing so, the fast dynamic MUX significantly improves the overall delay of the high-fan-in comparators. At the same time, a novel high-performance static priority encoder is proposed to generate the control signal for the MUX. A 64-bit MUX-based comparator has been built and compared with the existing fastest single-cycle design in the study by Lam and Tsui (2006). From both the post-layout simulation and test-chip measurement results, it is shown that the performance is improved by around 28%. View full abstract»

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  • Application-Specific Instruction-Set Processor for Retinex-Like Image and Video Processing

    Page(s): 596 - 600
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (675 KB) |  | HTML iconHTML  

    This brief presents an application-specific instruction-set processor (ASIP) for real-time Retinex image and video filtering. Design optimizations are addressed at algorithmic and architectural levels, the latter including a dedicated memory structure, an adapted pipeline, bypasses, a custom address generator and special looping structures. Synthesized in CMOS technology, the ASIP stands for its better energy-flexibility tradeoff versus reference ASIC and digital signal processing Retinex implementations. View full abstract»

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  • Slew-Rate-Controlled Output Driver Having Constant Transition Time Over Process, Voltage, Temperature, and Output Load Variations

    Page(s): 601 - 605
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (867 KB) |  | HTML iconHTML  

    A slew-rate-controlled output driver having a constant transition time irrespective of environmental variations is described in this brief. The proposed output driver employs a capacitive feedback between the output and input of the driver to allow its transition time independent of process, voltage, temperature and output load variations. The proposed output driver was designed and fabricated using a 0.13-mum CMOS process. According to our experimental results, the normalized variation on transition time of the proposed output driver due to PVT variations was improved by 74%-80% as compared to the conventional output driver. The comparison result also indicates that the normalized variation on transition time due to output load change from 10 to 100 pF (10 times variation) in typical process, voltage and temperature corners was improved by up to 66%. View full abstract»

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  • High-Throughput Memory-Based Architecture for DHT Using a New Convolutional Formulation

    Page(s): 606 - 610
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (227 KB) |  | HTML iconHTML  

    A new formulation is presented for the computation of an -point discrete Hartley transform (DHT) from two pairs of [(N/2-1)/2]-point cyclic convolutions, and further used to obtain modular structures consisting of simple and regular memory-based systolic arrays for concurrent pipelined realization of the DHT. The proposed structures for direct-memory-based implementation is found to involve nearly the same hardware complexity as those of the existing structures, but offers two to four times more throughput and two to four times less latency compared with others. The distributed-arithmetic (DA)-based implementation is also found to offer very less memory-complexity and considerably low area-delay complexity compared with the existing DA-based structures. View full abstract»

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  • Half-Delay B-Spline Filter for Construction of Shift-Invariant Wavelet Transform

    Page(s): 611 - 615
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (158 KB) |  | HTML iconHTML  

    We introduce a general framework for the shift-invariant biorthogonal wavelet transform. The method is based on the two parallel wavelet transforms, where the wavelets form a Hilbert transform pair. This condition requires that the impulse responses of the scaling filters are half-delayed versions of each other:ho [n] and ho [n-1/2]. The ideal half-delay operator is constructed by the interpolation and decimation procedure based on the polyphase decomposition of the two-scale B-spline equation. The present method yields linear phase and shift-invariant wavelet transform coefficients and can be adapted to any of the existing biorthogonal DWT filter bank. View full abstract»

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  • Reconstruction of Two-Periodic Nonuniformly Sampled Band-Limited Signals Using a Discrete-Time Differentiator and a Time-Varying Multiplier

    Page(s): 616 - 620
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (223 KB) |  | HTML iconHTML  

    This brief considers the problem of reconstructing a band-limited signal from its two-periodic nonuniformly spaced samples. We propose a novel reconstruction system where a finite-impulse response filter designed as differentiator followed by a time-varying multiplier recovers the uniformly spaced from the nonuniformly spaced samples. The system roughly doubles the signal-to-noise ratio with relatively few filter coefficients. The main advantage is that once the differentiator has been designed, it can be implemented with fixed multipliers, and only the coefficients of the time-varying multiplier have to be adapted when the sampling pattern changes; this reduces implementation costs substantially. In addition, the system allows an efficient polyphase implementation. View full abstract»

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  • An Efficient Variable Gain Homotopy Method Using the SPICE-Oriented Approach

    Page(s): 621 - 625
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (173 KB) |  | HTML iconHTML  

    Homotopy methods are known to be effective methods for finding dc operating points of nonlinear circuits with the theoretical guarantee of global convergence. There are several types of homotopy methods; as one of the efficient methods for solving bipolar circuits, the variable gain homotopy (VGH) method is well-known. However, in the conventional VGH method, the initial point is sometimes far from the solution because it is given as a solution of a diode circuit. In this brief, we propose an efficient VGH method using the SPICE-oriented approach. The proposed method can be easily implemented on SPICE without programming, although we do not know the homotopy method well. Moreover, since we can use a good initial point, the path following tends to become smooth and efficient. View full abstract»

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  • Improved Sufficient Conditions for Global Asymptotic Stability of Delayed Neural Networks

    Page(s): 626 - 630
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (143 KB) |  | HTML iconHTML  

    This brief addresses the global asymptotic stability (GAS) of delayed neural networks. Based on the Lyapunov method, using some existing results for the existence and uniqueness of the equilibrium point, some sufficient conditions are obtained for checking the GAS without demanding the boundedness and differentiability hypotheses for activation functions. Through comparison, it is illustrated that our conditions extend and improve some recent results. View full abstract»

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  • Design and Implementation of MIMO-OFDM Baseband Processor for High-Speed Wireless LANs

    Page(s): 631 - 635
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (775 KB) |  | HTML iconHTML  

    In this brief, we present the design and implementation results of a digital 120 Mb/s multiple-input multiple-output (MIMO) orthogonal frequency-division multiplexing (OFDM) wireless LAN (WLAN) baseband processor based on the proposed decoding algorithms. The processor has two MIMO-OFDM modes, space-frequency block coded OFDM and space division multiplexed OFDM. From those, it achieves a considerable performance gain as well as supports double data rates compared to the conventional IEEE 802.11a WLANs. In the results of performance evaluation, the processor requires a signal-to-noise ratio of 1.8-27 dB for transmission modes at 10% packet error rate, and the chip is implemented with 4.8 M transistors in 3.9 times 3.9 mm2 using 0.18-mum CMOS process. View full abstract»

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  • Very Low-Complexity Hardware Interleaver for Turbo Decoding

    Page(s): 636 - 640
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    This brief presents a very low complexity hardware interleaver implementation for turbo code in wideband CDMA (W-CDMA) systems. Algorithmic transformations are extensively exploited to reduce the computation complexity and latency. Novel VLSI architectures are developed. The hardware implementation results show that an entire turbo interleave pattern generation unit consumes only 4 k gates, which is an order of magnitude smaller than conventional designs. View full abstract»

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  • Automatic Substrate Switching Circuit for On-Chip Adaptive Power-Supply System

    Page(s): 641 - 645
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (991 KB) |  | HTML iconHTML  

    In energy-aggressive dynamic voltage scaling techniques, adaptive on-chip power supply, which can provide variable voltage in a wide range, is highly demanded. However, potential leakage and latch-up problems arise, when the substrate biasing voltages of the transistors vary with the supply voltage. An automatic substrate switching circuit (ASSC) is thus presented in this paper, with accurate voltage comparison, fast transient response and small silicon area. Experimental results show that the circuit automatically and accurately switches 1.3-nF pMOS substrate at a switching speed of 1.1 V/mus, with a switching voltage range of 1.1 to 3.3 V. The tracking error in steady state is below 18 mV. Fabricated in a standard 0.35-mum n-well digital CMOS process, the ASSC circuit only requires 0.017 mm 2 silicon areas, with a maximum static power of 116 muW. View full abstract»

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  • Special issue on multifunctional circuits and systems for future generations of wireless communications

    Page(s): 646
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  • 2008 IEEE International Symposium on Circuits and Systems-engineering the environmental revolution (ISCAS 2008)

    Page(s): 647
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  • IEEE Transactions on Circuits and Systems—II: Express Briefs Information for authors

    Page(s): 648
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  • IEEE Circuits and Systems Society Information

    Page(s): C3
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Aims & Scope

TCAS II publishes brief papers in the field specified by the theory, analysis, design, and practical implementations of circuits, and the application of circuit techniques to systems and to signal processing. Included is the whole spectrum from basic scientific theory to industrial applications. The field of interest covered includes:

  • Circuits: Analog, Digital and Mixed Signal Circuits and Systems  
  • Nonlinear Circuits and Systems, Integrated Sensors, MEMS and Systems on Chip, Nanoscale Circuits and Systems, Optoelectronic
  • Circuits and Systems, Power Electronics and Systems
  • Software for Analog-and-Logic Circuits and Systems
  • Control aspects of Circuits and Systems. 

Full Aims & Scope