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IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems

Issue 8 • Date Aug. 2007

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  • Table of contents

    Publication Year: 2007, Page(s):C1 - C2
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  • IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems publication information

    Publication Year: 2007, Page(s): C2
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  • Remembering Richard [Obituary, Richard A.Newton]

    Publication Year: 2007, Page(s):1357 - 1366
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  • DC–DC Converter-Aware Power Management for Low-Power Embedded Systems

    Publication Year: 2007, Page(s):1367 - 1381
    Cited by:  Papers (62)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (765 KB) | HTML iconHTML

    Most digital systems are equipped with dc-dc converters to supply various levels of voltages from batteries to logic devices. DC-DC converters maintain legal voltage ranges regardless of the load current variation as well as battery voltage drop. Although the efficiency of dc-dc converters is changed by the output voltage level and the load current, most existing power management techniques simply... View full abstract»

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  • TermMerg: An Efficient Terminal-Reduction Method for Interconnect Circuits

    Publication Year: 2007, Page(s):1382 - 1392
    Cited by:  Papers (8)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (786 KB) | HTML iconHTML

    In this paper, a novel method to efficiently reduce the terminal number of general linear-interconnect circuits with a large number of input or output terminals considering delay uncertainty is proposed. Our new algorithm is motivated by the fact that terminal reduction can lead to a more compact order-reduced model and the observation that very large-scale integration interconnect circuits have m... View full abstract»

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  • Realizable Reduction of RC Networks

    Publication Year: 2007, Page(s):1393 - 1407
    Cited by:  Papers (9)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (371 KB) | HTML iconHTML

    In this paper, we develop from various points of view the time-constant equilibration reduction (TICER) algorithm, a circuit-reduction method that converts a given network into a smaller network (one with fewer nodes and branches) by eliminating nodes that have few neighbors and small nodal time constants. Advantages of TICER include: great efficiency, intuitive error control, preservation of spar... View full abstract»

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  • Discretization of Macroscopic Transport Equations on Non-Cartesian Coordinate Systems

    Publication Year: 2007, Page(s):1408 - 1416
    Cited by:  Papers (1)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (301 KB) | HTML iconHTML

    We discuss discretization schemes for the Poisson equation, the isothermal drift-diffusion equations, and higher order moment equations derived from the Boltzmann transport equation for general coordinate systems. We briefly summarize the method of dimension reduction when the problem does not depend on one coordinate. Discretization schemes for dimension-reduced coordinate systems are introduced,... View full abstract»

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  • A Network-Flow-Based RDL Routing Algorithmz for Flip-Chip Design

    Publication Year: 2007, Page(s):1417 - 1429
    Cited by:  Papers (31)  |  Patents (1)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (1517 KB) | HTML iconHTML

    The flip-chip package gives the highest chip density of any packaging method to support the pad-limited application-specific integrated circuit designs. In this paper, we propose the first router for the flip-chip package in the literature. The router can redistribute nets from wire-bonding pads to bump pads and then route each of them. The router adopts a two-stage technique of global routing fol... View full abstract»

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  • MB-Tree: A Multilevel Floorplanner for Large-Scale Building-Module Design

    Publication Year: 2007, Page(s):1430 - 1444
    Cited by:  Papers (2)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (874 KB) | HTML iconHTML

    In this paper, we present an agglomeratively multilevel floorplanning/placement framework based on the B -tree representation called MB- tree to handle the floorplanning and packing for large-scale building modules. The MB-tree adopts a two-stage technique, i.e., clustering followed by declustering. The clustering stage iteratively groups a set of modules based on a cost metric guided by area util... View full abstract»

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  • Optimal Jumper Insertion for Antenna Avoidance Considering Antenna Charge Sharing

    Publication Year: 2007, Page(s):1445 - 1453
    Cited by:  Papers (5)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (294 KB) | HTML iconHTML

    Antenna effect may damage gate oxides during a plasma-based fabrication process. The antenna ratio of total exposed antenna area to total gate oxide area is directly related to the amount of damage. Jumper insertion is a common technique applied at routing and post-layout stages to avoid and to fix the problems caused by the antenna effect. This paper presents an optimal algorithm for jumper inser... View full abstract»

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  • BMSYN: Bus Matrix Communication Architecture Synthesis for MPSoC

    Publication Year: 2007, Page(s):1454 - 1464
    Cited by:  Papers (15)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (1579 KB) | HTML iconHTML

    Modern multiprocessor system-on-chip designs have high bandwidth constraints which must be satisfied by the underlying communication architecture. Traditional hierarchical shared bus communication architectures can only support limited bandwidths and are not scalable for very high-performance designs. Bus matrix-based communication architectures consist of several parallel busses which provide a s... View full abstract»

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  • Statistical Test Development for Analog Circuits Under High Process Variations

    Publication Year: 2007, Page(s):1465 - 1477
    Cited by:  Papers (18)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (472 KB) | HTML iconHTML

    The test development efforts for analog circuits today are disproportionately high due to the lack of widely accepted automation methods. The evaluation of a particular test input and measurement setup requires the determination of the probabilistic detection of all faults in the circuit. This evaluation step is the most time consuming step during analog test development. Based on the observation ... View full abstract»

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  • Fault Diagnosis With Convolutional Compactors

    Publication Year: 2007, Page(s):1478 - 1494
    Cited by:  Papers (10)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (634 KB) | HTML iconHTML

    This paper presents new nonadaptive fault-diagnosis techniques for scan-based designs. They guarantee accurate and time-efficient identification of failing scan cells based on results of convolutional compaction of test responses. The essence of the method is to use a branch-and-bound algorithm to narrow the set of scan cells down to certain sites that are most likely to capture faulty signals. Th... View full abstract»

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  • Parameterized Non-Gaussian Variational Gate Timing Analysis

    Publication Year: 2007, Page(s):1495 - 1508
    Cited by:  Papers (1)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (390 KB) | HTML iconHTML

    As technology scales down, timing verification of digital integrated circuits becomes an extremely difficult task due to the gate and wire variability. Therefore, statistical timing analysis (denoted by sigmaTA) is becoming unavoidable. In this paper, two new approaches for doing variational gate TA for Gaussian and non-Gaussian sources of variation in parameterized sigmaTA are presented. To start... View full abstract»

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  • Observability Analysis on HDL Descriptions for Effective Functional Validation

    Publication Year: 2007, Page(s):1509 - 1521
    Cited by:  Papers (2)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (631 KB) | HTML iconHTML

    Simulation-based functional validation is still one of the primary approaches for verifying designs described in hardware description languages. Traditional code coverage metrics do not address the observability issue and may overestimate the extent of functional validation. Observability-based code coverage metric (OCCOM) is the first code coverage metric considering the essential observability i... View full abstract»

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  • Advances in Computation of the Maximum of a Set of Gaussian Random Variables

    Publication Year: 2007, Page(s):1522 - 1533
    Cited by:  Papers (17)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (718 KB) | HTML iconHTML

    This paper quantifies the approximation error when results obtained by Clark (1961) are employed to compute the maximum (max) of Gaussian random variables, which is a fundamental operation in statistical timing. We show that a finite lookup table can be used to store these errors. Based on the error computations, approaches to different orderings for pairwise max operations on a set of Gaussians a... View full abstract»

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  • On an Efficient CAD Implementation of the Distance Term in Pelgrom's Mismatch Model

    Publication Year: 2007, Page(s):1534 - 1538
    Cited by:  Papers (4)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (225 KB) | HTML iconHTML

    In 1989, Pelgrom et al. published a mismatch model for MOS transistors, where the variation of parameter mismatch between two identical transistors is given by two independent terms: a size-dependent term and a distance-dependent term. Some CAD tools based on a nonphysical interpretation of Pelgrom's distance term result in excessive computationally expensive algorithms, which become nonviable eve... View full abstract»

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  • Test Wrapper Design and Optimization Under Power Constraints for Embedded Cores With Multiple Clock Domains

    Publication Year: 2007, Page(s):1539 - 1547
    Cited by:  Papers (4)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (495 KB) | HTML iconHTML

    Even though many embedded cores contain several clock domains, most published methods for wrapper design have been limited to single-frequency cores. Cumbersome and invasive design techniques, such as insertion of test points, are needed to make these methods applicable to current-generation embedded cores. This paper presents a new method for designing test wrappers for embedded cores with multip... View full abstract»

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  • IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems Information for authors

    Publication Year: 2007, Page(s): 1548
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  • IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems society information

    Publication Year: 2007, Page(s): C3
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Aims & Scope

The purpose of this Transactions is to publish papers of interest to individuals in the area of computer-aided design of integrated circuits and systems composed of analog, digital, mixed-signal, optical, or microwave components.

Full Aims & Scope

Meet Our Editors

Editor-in-Chief

VIJAYKRISHNAN NARAYANAN
Pennsylvania State University
Dept. of Computer Science. and Engineering
354D IST Building
University Park, PA 16802, USA
vijay@cse.psu.edu