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Electronics Packaging Manufacturing, IEEE Transactions on

Issue 2 • Date April 2007

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Displaying Results 1 - 16 of 16
  • Table of contents

    Page(s): C1
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  • IEEE Transactions on Electronics Packaging Manufacturing publication information

    Page(s): C2
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  • Scheduling Integrated Circuit Assembly Operations on Die Bonder

    Page(s): 97 - 105
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (733 KB) |  | HTML iconHTML  

    Solving the integrated circuit (IC) assembly scheduling problem (ICASP) is a very challenging task in the IC manufacturing industry. In the IC assembly factories, the jobs are assigned processing priorities and are clustered by their product types, which must be processed on groups of identical parallel machines. Furthermore, the job processing time depends on the product type, and the machine setup time is sequentially dependent on the orders of jobs processed. Therefore, the ICASP is more difficult to solve than the classical parallel machine scheduling problem. In this paper, we describe the ICASP in detail and formulate the ICASP as in integer programing problem to minimize the total machine workload. An efficient heuristic algorithm is also proposed for solving large-scale problems. View full abstract»

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  • Testing and Evaluation of Silicon Die Strength

    Page(s): 106 - 114
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (1593 KB) |  | HTML iconHTML  

    In the applications of 3-D packages or stacked die packages, mostly the silicon wafers have to be ground thinner, and then the strengths of the dies from the wafers are needed for assuring good design and reliability of the packages. The purposes of this study are twofold: one is to attempt to develop a new, suitable test method for differentiating the factors that affect the variability of die strength, and the other is to investigate the failure and fatigue strengths of silicon dies. In this paper, a new test method, a plate-on-elastic-foundation test (PEFT) associated with point- or line-loading has been proposed and evaluated. It is found that the PEFT can provide not only a simple, chipping-free test for dummy or real IC chips without limitation of size, but also a (bi-axial) stress field similar to the temperature loading. The strength data of failures on IC and ground surfaces in real IC chips are presented. The good consistency of the die strength data with a minor scatter from both the point- and line-load tests is found for the specimens failed on IC surfaces, but not for the ones failed on the ground surfaces. The inconsistency of strength data from both tests for failure on ground surfaces is due to edge chipping involved. The large scatter is caused by the combined factors of the angle of grinding marks, planes of weakness of material, and loading stress states with uni-axial stress for line-load test and with unequal bi-axial stress for point-load test of rectangular specimens. The surface roughness of the dies (including the IC and ground surfaces) measured by atomic force microscopy is correlated with the failure modes and strengths from the tests. It is found that the silicon die strengths are dominated by the roughness on failure surfaces, and their failure modes always appear cracks along the directions parallel and normal to the edges of the die, which might be the weak plane of the crystal lattice of silicon. The specimens with artificial cracks- have been further tested. It has been proved that the die strength dominated by the crack initiation depends on the most severe defect but not on the amount of the defects, and its failure mode is controlled by a special weak plane after the crack initiation. Conclusively, there are four factors to influence die strength: the surface conditions of the die (including grinding-mark direction and surface roughness), the edge crack of the die (so-called chipping created during the cutting process), the weak planes of the crystal lattice of silicon, and, sometimes, different tests with various loading conditions. The fatigue strength of the die is also determined to be about 25% lower than the static one. View full abstract»

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  • Surface Resistivity Characterization of New Printed Circuit Board Materials for Use in Spacecraft Electronics

    Page(s): 115 - 122
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (1505 KB) |  | HTML iconHTML  

    New dielectric materials have been introduced for printed circuit board applications, such as Thermount and polyimide with the aim to match the requirements for high speed and high density of electronic devices that are planned for new spacecraft electronic boards. Before these newer substrate can fully replace the well-known space-approved material epoxy FR-4, it is necessary to investigate more deeply their electrical and mechanical properties. The scope of this study is to report quantitative characterization of the surface resistivity for the different material samples under various testing conditions that include relative humidity, temperature, solder flux contamination, and corona discharge. The surface resistivity results are reported for sets of samples measured under a combination of testing conditions. View full abstract»

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  • A Copper/Polyimide Fabrication Process for Fabricating High-Inductance Microinductor

    Page(s): 123 - 127
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (452 KB) |  | HTML iconHTML  

    This paper reports on a technological process that combines copper as conductor, permalloy as magnetic core material, and polyimide as insulation material to complete a microinductor on glass with high inductance. The shape of the magnetic core scheme was rectangular, of which the width of the long side and short side were 1.4 and 0.6 mm, respectively. The dimensions of the inductor are 3.86 mm times 3.94 mm times 90 mum with coil width of 20 mum and space of 35 mum. The results show that the maximum inductance is 4 muH at 1 MHz, and the maximum quality factor (Q-factor) is 1.5 at 2 MHz. View full abstract»

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  • Assessment of Thermomechanical Damage of Electronic Parts Due to Solder Dipping as a Postmanufacturing Process

    Page(s): 128 - 137
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (1133 KB) |  | HTML iconHTML  

    Tin whiskering is a concern with tin-rich alloy finishes on electronic part terminations. Solder dipping may be used to replace the original finish with eutectic tin-lead solder for tin-whiskering risk mitigation purposes. However, the solder dipping process may expose electronic parts to thermomechanical damage within the package due to the thermal refinishing profile used during dipping. This paper discusses solder dipping as a refinishing technique and the associated risks from thermomechanical damage. An experimental study was used to assess the possibility of thermomechanical damage on various electronic part-types of different package configurations. Package and die geometries were characterized for all part-types to develop quantitative metrics, which may be used by electronic part users to assess parts for their susceptibility to thermomechanical damage. View full abstract»

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  • Forward and Backward Compatibility of Solder Alloys With Component and Board Finishes

    Page(s): 138 - 146
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (1671 KB) |  | HTML iconHTML  

    The primary objective of the research presented in this paper is to qualify the reliability of mixed assemblies by comparing them to the conventional Sn-Pb assembly and completely Pb-free assembly. The research investigates both forward and backward compatibility in electronic assemblies using a design of experiments (DOE) approach. The investigation utilized a test vehicle containing an area array component (BGA169) and chip components (0603 resistors). Hot air solder leveling (HASL) and organic solderability preservative (OSP) surface finishes were used on the test vehicles to represent Sn-Pb and Pb-free alternatives, respectively. The assembled test vehicles were cut into two panels - one containing a resistor section for isothermal aging and the other containing a BGA and another resistor section for thermal shock. The assemblies were subjected to isothermal aging and thermal shock tests as per Interconnecting and Packaging Electronic Circuits/Joint Electronic Device Engineering Council (IPC/JEDEC) standards. The resistors were sheared in the "as-soldered" condition, and at various isothermal aging intervals and thermal shock cycles. In order to simulate an intermetallic failure in isothermal aging, a reduced shear height (20 mum) was used for the shear test. The performance of the resistor solder joints were quantified in terms of the shear force. The performance of the ball grid array (BGA) solder joint during thermal shock testing was quantified in terms of the number of cycles to failure. Experimental results from shear analysis of resistor solder joints show that Pb-free alloy assemblies' performance is superior to those assembled using Sn-Pb alloy. Also, the ductile nature of the Sn-Ag-Cu (SAC) alloy provides the joints a better fatigue life. With the area array components, Pb-free assembly joints outlived the traditional Sn-Pb joints when subjected to thermal shock loading. Among the mixed assemblies, backward-compatible assemblies (Pb-free bumps and Sn-- Pb solder alloy) showed superior performance. The microstructural analysis of the solder joints indicate a uniform distribution of lead in the solder joint matrix. View full abstract»

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  • Fast Heuristics for Designing Integrated E-Waste Reverse Logistics Networks

    Page(s): 147 - 154
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (438 KB) |  | HTML iconHTML  

    This paper investigates a mixed-integer linear programming model that solves an integrated facility location and configuration problem for recycling electronic waste (e-waste). Since different recycled e-waste consume different levels of recycling processes and resources, the capability of processing only one or more categories of recycled e-waste for each candidate facility is considered in addition to its location to maximize the total revenue. Computational experiments based on proposed heuristics are conducted using data collected from Taiwan's recycled e-waste market and show our proposed methods give a high-quality near-optimal solution in a promising time shorter than previous solution methods and CPLEX. View full abstract»

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  • Fluxless Wafer Bonding in Vacuum Using Electroplated Sn–Ag Layers

    Page(s): 155 - 159
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (1074 KB) |  | HTML iconHTML  

    A wafer-to-wafer bonding process using Sn-Ag solder without any flux is successfully developed. This fluxless or flux-free feature makes void-free and uniform bonding layers possible. This is in contrast to the fluxing process employed in nearly all soldering processes adapted in the electronic industry. With the use of flux, the flux or flux residues are easily trapped in the solder joint, resulting in voids and uneven solder layers. This is particularly true if the bonding area is large, such as the entire wafer. Thus, void-free wafer bonding using solders has never been reported. It is thus clear that the key to achieve void-free wafer soldering is to eliminate flux completely. The new fluxless process is performed in a vacuum furnace built in house to inhibit solder oxidation. To prevent oxidation during solder manufacturing, a thin Ag capping layer is plated over the Sn layer right after the Sn layer is plated over an entire 2-in silicon wafer having Cr/Au under bump metallurgy (UBM). This outer Ag layer is critical in preventing the inner Sn layer from oxidation when the wafer is exposed to air. The Si wafer with Cr/Au/Sn/Ag structure is bonded with another Si wafer with Cr/Au at 240degC in the vacuum furnace. To evaluate the joint quality and study the microstructure and composition, scanning acoustic microscopy (SAM), scanning electron microscopy (SEM), and energy dispersive X-ray spectroscopy (EDX) are used. A solder joint with only 1% void area is accomplished. The initial success of this process illustrates that it is indeed possible to bond entire wafers together with a thin metallic joint of high quality. This fluxless bonding technique can be extended to bonding wafers of different materials for new device and packaging applications. View full abstract»

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  • Development of Analog Optohybrid Circuit for the CMS Inner Tracker Data Acquisition System: Project, Quality Assurance, Volume Production, and Final Performance

    Page(s): 160 - 167
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (2659 KB) |  | HTML iconHTML  

    The tracker system of the compact muon solenoid (CMS) experiment, will employ approximately 40000 analog fiber-optic data and control links. The optical readout system is responsible for converting and transmitting the electrical signals coming out from the front-end to the outside counting room. Concerning the inner part of the Tracker, about 3600 analog optohybrid circuits are involved in this tasks. These circuits have been designed and successfully produced in Italy under the responsibility of INFN Perugia CMS group, completing the volume production phase by February 2005. Environmental features, reliability, and performances of the analog optohybrid circuits have been extensively tested and qualified. This paper reviews the most relevant steps of the manufacturing and quality assurance process: from prototypes to mass-production for the final use in the CMS data acquisition system. View full abstract»

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  • Quality without compromise [advertisement]

    Page(s): 168
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  • Table of contents

    Page(s): 169 - 170
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  • Table of contents

    Page(s): 171 - 172
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  • IEEE Components, Packaging, and Manufacturing Technology Society Information for authors

    Page(s): C3
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  • IEEE Components, Packaging, and Manufacturing Technology Society Information

    Page(s): C4
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Aims & Scope

IEEE Transactions on Electronics Packaging Manufacturing addresses design for manufacturability, cost and process modeling, process control and automation, factory analysis and improvement, information systems, statistical methods, environmentally friendly processing, and computer-integrated manufacturing for the production of electronic assemblies and products.

 

This Transaction ceased production in 2010. The current publication is titled IEEE Transactions on Components, Packaging, and Manufacturing Technology.

Full Aims & Scope

Meet Our Editors

Editor-in-Chief
R. Wayne Johnson
Auburn University