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Electron Device Letters, IEEE

Issue 7 • Date July 2007

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Displaying Results 1 - 25 of 47
  • Table of contents

    Page(s): C1 - 538
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  • IEEE Electron Device Letters publication information

    Page(s): C2
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  • Metamorphic Heterostructure InP/GaAsSb/InP HBTs on GaAs Substrates by MOCVD

    Page(s): 539 - 542
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    Good-quality metamorphic InP buffer layers have been successfully grown on GaAs substrates by metal-organic chemical vapor deposition. Characterization by atomic force microscope, transmission electron microscopy, high-resolution X-ray diffraction, and Hall measurements indicated that the layers are of high crystalline quality, good mobility, and excellent surface morphology. On this buffer, we demonstrated the first metamorphic InP/GaAsSb/InP double heterojunction bipolar transistors (DHBTs) with good material quality and device performance. Metamorphic DHBTs showed direct-current and radio-frequency characteristics that are comparable to those grown on lattice-matched InP substrates. View full abstract»

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  • Improved Stability of High-Performance ZnO/ZnMgO Hetero-MISFETs

    Page(s): 543 - 545
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    Improved performance and stability was demonstrated for ZnO/ZnMgO hetero-MISFETs. The MIS gate structures that were formed using either a 50-nm-thick Al2O3 or HfO2 gate dielectric layer were examined by observation of the transfer characteristic hysteresis. A significantly reduced hysteresis of less than 0.1 V was obtained for HfO2 as compared to that for the Al2O3 gate dielectric. By reducing the access resistance, the 1-mum gate devices showed improved transconductance values, as high as 54 mS/mm for Al2O3 and 71 mS/mm for HfO2, which are the highest values ever reported for ZnO-based FETs. View full abstract»

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  • 50-nm T-Gate InAlAs/InGaAs Metamorphic HEMTs With Low Noise and High fT Characteristics

    Page(s): 546 - 548
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    We report 50-nm T-gate metamorphic high-electron mobility transistors (MHEMTs) with low noise figure and high characteristics. The 30 mumtimes2 MHEMT shows a drain current density of 690 mA/mm, a gm,max of 1270 mS/mm, an fT of 489 GHz, and an of 422 GHz. In the frequency range of 59-61 GHz, the noise figure is less than 0.7 dB, and the associated gain was greater than 9 dB at a drain voltage of 1.3 V and a gate voltage of -0.8 V. To our knowledge, the MHEMT shows the best performance in terms of and noise figure among GaAs-based HEMTs. View full abstract»

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  • AlGaN/GaN HEMTs With Thin InGaN Cap Layer for Normally Off Operation

    Page(s): 549 - 551
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    AlGaN/GaN HEMTs with a thin InGaN cap layer have been proposed to implement the normally off HEMTs. The key idea is to employ the polarization-induced field in the InGaN cap layer, by which the conduction band is raised, which leads to the normally off operation. The fabricated HEMT with an In0.2Ga0.8N cap layer with a thickness of 5 nm showed normally off operation with a threshold voltage of 0.4 V and a maximum transconductance of 85 mS/mm for the device with a 1.9-mum-long gate. By etching off the In0.2Ga0.8N cap layer at the access region using gate electrode as an etching mask, the maximum transconductance has increased from 85 to 130 mS/mm due to a reduction of the parasitic source resistance. View full abstract»

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  • Design and Fabrication of Elastic Interconnections for Stretchable Electronic Circuits

    Page(s): 552 - 554
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    For biomedical and textile applications, the comfort of the user will be enhanced if the electronic circuits are not only flexible but also elastic. This letter reveals a simple moulded-interconnect-device technology for the construction of elastic point-to-point interconnections, based on 2-D spring-shaped metallic tracks, which are embedded in a highly elastic silicone film. Metal interconnections of 3-cm long were constructed with an initial resistance of about 3Omega , which did not significantly increase (<5%) when stretched. A stretchability above 100% in one direction has been demonstrated. View full abstract»

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  • Characteristics of Ni/Gd FUSI for NMOS Gate Electrode Applications

    Page(s): 555 - 557
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    This letter investigates the work function tuning of nickel/gadolinium (Ni/Gd) fully silicided (FUSI) gate electrodes on HfSiOx dielectrics. It was found that as the percentage of Gd in the Ni/Gd increased from 10% to 30%, the effective work function value after a one-step 450-degC FUSI anneal decreased from 4.75 to 4.35 eV. In addition, the presence of Gd also resulted in lowering of equivalent oxide thickness (EOT) values. The mechanism for a decreased EOT is attributed to the reduction of low-kappa interfacial layers by the presence of Gd in the gate stack. The decrease in work function is attributed to the creation of oxygen vacancies within the high-kappa layer created by the presence of Gd layer. View full abstract»

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  • Observation of Metal-Layer Stress on Si Nanowires in Gate-All-Around High- κ/Metal-Gate Device Structures

    Page(s): 558 - 561
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    This letter reports, for the first time, the observation of mechanical stress from metal-gate layer on the Si nanowires formed by the top-down scheme. High-kappa (HfO2 ~ 5 nm) and metal-gate (TaN ~ 100 nm) are evaluated on Si nanowires having ~5-7 nm diameter. While no significant mechanical effect is observed after high-kappa deposition, the TaN metal layer is found to viciously stretch and twist the straight wires. The wire lengths increase significantly (~3%), which suggests that the Si nanowires are subjected to large tensile strain ( > 4 GPa), assuming that the wires obey Hooke's law with Young's modulus ~150 GPa for bulk Si. Interestingly, the twisted nanowires maintained their physical continuity, as demonstrated by the excellent performance of the fully functional gate-all-around MOSFETs fabricated with the wires as channels. View full abstract»

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  • Ar Annealing for Suppression of Gate Oxide Thinning at Shallow Trench Isolation Edge

    Page(s): 562 - 564
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    We investigated the effects of high-temperature N2 and Ar annealing after sacrificial oxidation on the rounding of the top corners in shallow trench isolation (STI). With the N2 and Ar annealing, the corners were rounded, and the gate oxide thinning was suppressed, indicating that high-temperature annealing in an inert gas ambient is effective for rounding the corners and increasing the gate oxide thickness. With the N2 annealing, however, the hump in the Id-Vg curve increased, and the time-dependent dielectric breakdown (TDDB) characteristics were degraded. The possible reason is that the suppression of gate oxidation and/or the oxide quality change occurs at the local spots at the top corners due to the introduction of nitrogen. With the Ar annealing, there was no hump, and the TDDB characteristics improved. It is presumed that the Ar did not accumulate at the sacrificial oxide/substrate interface. Therefore, Ar annealing after gap filling is promising in improving the performance and reliability of transistors with STI. View full abstract»

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  • Schottky-Barrier Height Tuning by Means of Ion Implantation Into Preformed Silicide Films Followed by Drive-In Anneal

    Page(s): 565 - 568
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    An experimental study on Schottky-barrier height (SBH) tuning using ion implantation followed by drive-in anneal of As, B, In, and P in preformed NiSi and PtSi films is presented. Measured on B-implanted NiSi and PtSi Schottky diodes, the effective SBH on n-type Si is altered to ~1.0 eV. For As- and P-implanted diodes, the SBH on p-type Si can be tuned to around 0.9 eV. The process window for the most pronounced SBH modification is dopant dependent. View full abstract»

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  • Carrier Transport Mechanism in a Nanoparticle-Incorporated Organic Bistable Memory Device

    Page(s): 569 - 571
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    In this letter, the conduction mechanism in nanoparticle-contained polymer memory was investigated experimentally and theoretically. The current-voltage characteristics showed that the device switches from an initial low-conductivity state to a high-conductivity state upon application of an external electric field at room temperature. The current transition exhibited a very narrow voltage range that causes an abrupt increase of current. A trap-filled space-charge-limited current model was proposed and supported by the experimental data to explain the transport mechanism in organic memory. View full abstract»

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  • Nonvolatile Multilevel Conductance and Memory Effect in Molecule-Based Devices

    Page(s): 572 - 574
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    Electrical characteristics of a single-layer organic device using 2-(hexahydropyrimidin-2-ylidene)-malononitrile (HPYM) that is interposed between Al/Al2O3 (cathode) and Ag (anode) electrodes were investigated. The application of different positive voltages produced different high-conductance currents, resulting in the multilevel memory capability of the device. The high-conductance states could be erased back to the low-conductance state by the application of a negative bias. The formation of an aluminum oxide layer between Al and HPYM layer could be one effective method to increase the data-retention time but could be irrelevant with the electric-field-induced conductance-state transition of the device. View full abstract»

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  • A Novel Silicon Photovoltaic Cell Using a Low-Temperature Quasi-Epitaxial Silicon Emitter

    Page(s): 575 - 577
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    A new silicon solar cell fabricated using a low-temperature process is demonstrated with a highly conductive (n+) quasi-epitaxial (qEpi-Si) silicon emitter deposited on silicon substrates, without using transparent conductive oxides. The emitter was formed by a plasma-enhanced chemical vapor deposition process on granular multicrystalline silicon (mc-Si) substrates at a substrate temperature of 250 . The new qEpi-Si/(p)mc-Si junction was found to be of good quality for photovoltaic applications. Solar cells of 1- area and conversion efficiencies exceeding 10% have been fabricated in a simple fabrication process and device structure. View full abstract»

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  • Implementation of Side Effects in Thermal Characterization of RGB Full-Color LEDs

    Page(s): 578 - 580
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (151 KB) |  | HTML iconHTML  

    This letter presents a useful thermal-characterization method for RGB full-color light-emitting diodes (LEDs). The superposition method was employed to calculate thermal resistances of a high-power RGB full-color LED package to implement the side effect. Independent driving of a single chip in the RGB package clearly exhibited a side effect on the other two chips. It was shown that driving a red chip at 350 mA, current induced 4.8degC temperature rise for the green and blue chips, which is about 30% of the temperature rise in the red chip itself. A thermal-resistance-coupling matrix was structured and used for the calculation of the junction temperatures of the chips. It was demonstrated that the superposition method can be employed for an accurate prediction of the junction temperature rises for the RGB full-color LED package. View full abstract»

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  • Parasitic Bipolar Junction Transistors in a Floating-Gate MOSFET for Fluorescence Detection

    Page(s): 581 - 583
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    In this letter, we examined whether the parasitic bipolar junction transistors (BJTs) in the MOSFET fabricated by the standard CMOS process can play a role as a fluorescence detector. To suppress the action of two vertical parasitic BJTs, the gate and n-well were tied in the parasitic BJTs, and the body node was connected to the drain. The proposed device was compared with the inherent and the parasitic diodes in the MOSFET. It had 100 times higher photocurrents than the diodes in the MOSFET. In addition, it was applied for the detection of the fluorescent signal, and could detect near 10 nM of Alexa 546. Therefore, CMOS-process-compatible parasitic BJTs can be used as a photodetector in an integrated fluorescence detector. View full abstract»

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  • Low-Temperature Passivation of Amorphous-Silicon Thin-Film Transistors With Supercritical Fluids

    Page(s): 584 - 586
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    In this letter, supercritical CO2 (SCCO2) fluids technology is employed for the first time to effectively passivate the defect states in hydrogenated amorphous-silicon thin-film transistors (a-Si:H TFTs) at low temperature (150degC ). With the high transport and diffusion properties of fluids, it is proposed to act as a transporter in delivering the molecules into the amorphous-silicon film and repairing defect states by the molecules. In addition, the propyl alcohol is used as the surfactant between nonpolar-SCCO2 fluids and polar-H2O molecules for mingling H2O molecules uniformly with the SCCO2 fluids. After the treatment of SCCO2 fluids mixed with water and propyl alcohol, the a-Si:H TFT exhibited superior transfer characteristics and lower threshold voltage. The improvement in electrical characteristics could be verified by the significant reduction of density of states in the mobility gap of amorphous-silicon. View full abstract»

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  • A New Degradation Mechanism in High-Voltage SiC Power MOSFETs

    Page(s): 587 - 589
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    The phenomenon of recombination-induced stacking faults in high-voltage p-n diodes in SiC has been previously shown to increase the forward voltage drop due to reduction of minority carrier lifetime. In this paper, it has been shown that, for the first time, this effect is equally important in unipolar devices such as high-voltage MOSFETs. If the internal body diode is allowed to be forward biased during the operation of these devices, then the recombination-induced SFs will reduce the majority carrier conduction current and increase the leakage current in blocking mode. The effect is more noticeable in high-voltage devices where the drift layer is thick and is not expected to impact 600-1200-V devices. View full abstract»

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  • Observation of Threshold-Voltage Instability in Single-Crystal Silicon TFTs on Flexible Plastic Substrate

    Page(s): 590 - 592
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (161 KB) |  | HTML iconHTML  

    We report the first observation of threshold-voltage instability of single-crystal silicon (Si) thin-film transistors (TFTs) that are fabricated on low-temperature flexible plastic substrate. Single-crystal Si of 200-nm thickness is transferred from silicon-on-insulator (SOI) onto an indium-tin-oxide-coated polyethylene terephthalate host substrate after selectively removing the buried-oxide layer from the SOI. TFTs of n-type were then fabricated on the transferred single-crystal Si layer with 1.8-mum thick SU-8-2 epoxy as the gate dielectric layer. It is observed that the threshold voltage (Vth) of these TFTs shifts to higher and lower values under high positive and negative gate-voltage stress, respectively. A logarithmic time-dependence of the Vth shift at high bias stress was clearly indicated. These results suggest that the instability of the threshold voltage of the single-crystal Si TFTs is attributed to the charge trapping in the gate dielectric layer. View full abstract»

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  • Limits of Performance Gain of Aligned CNT Over Randomized Network: Theoretical Predictions and Experimental Validation

    Page(s): 593 - 595
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    Nanobundle thin-film transistors (NB-TFTs) that are based on random networks of single-walled carbon nanotubes are often regarded as high performance alternative to amorphous-Si technology for various macroelectronic applications involving sensors and displays. Here, we use stick-percolation model to study the effect of collective (stick) alignment on the performance of NB-TFTs. For long-channel TFT, small degree of alignment improves the drain current due to the reduction of average path length; however, near-parallel alignment degrades the current rapidly, reflecting the decrease in the number of connecting paths bridging the source/drain. In this paper, we 1) use a recently developed alignment technique to fabricate NB-TFT devices with multiple densities D, alignment thetas, stick length LS, and channel length LC; 2) interpret the experimental data with a stick- percolation model to develop a comprehensive theory of NB-TFT for arbitrary D,thetas, LS, and LC; and 3) demonstrate theoretically and experimentally the feasibility of fivefold enhancement in current gain with optimized transistor structure. View full abstract»

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  • Transport Mechanism of SiGe Dot MOS Tunneling Diodes

    Page(s): 596 - 598
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    The blockage of hole transport due to excess holes In SiGe dots was observed in the MOS tunneling diodes for the first time. The five layers of self-assembled SiGe dots are separated by 74-nm Si spacers and capped with a 130-nm Si. The hole tunneling current from Pt gate electrode to p-type Si dominates the inversion current at positive gate bias and is seven orders of magnitude higher than the Al gate/oxide/p-Si device. The large work function of Pt is responsible for the hole transport current from Pt to p-Si. The incorporation of SiGe dots confines the excess holes in the valence band and forms a repulsive barrier to reduce the hole transport current from Pt to SiGe dots by 2-3 orders of magnitude in comparison with the Pt/oxide/p-Si device. This repulsive barrier also reduces the hole tunneling current from SiGe dots to Pt at negative gate bias. View full abstract»

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  • High-Performance Self-Aligned Bottom-Gate Low-Temperature Poly-Silicon Thin-Film Transistors With Excimer Laser Crystallization

    Page(s): 599 - 602
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    In this letter, high-performance bottom-gate (BG) low-temperature poly-silicon thin-film transistors (TFT) with excimer laser crystallization have been demonstrated using self-aligned (SA) backside photolithography exposure. The grains with lateral grain size of about 0.75 mum could be artificially grown in the channel region via the super-lateral-growth phenomenon fabricated by excimer laser irradiation. Consequently, SA-BG TFT with the channel length of 1 mum exhibited field-effect mobility reaching 193 cm2/V ldr s without hydrogenation, while the mobility of the conventional non-SA-BG TFT and conventional SA top-gate one were about 17.8 and 103 cm2/V ldr s, respectively. Moreover, SA-BG TFT showed higher device uniformity and wider process window owing to the homogenous lateral grains crystallized from the channel steps near the BG edges. View full abstract»

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  • Flicker Noise and Its Degradation Characteristics Under Electrical Stress in MOSFETs With Thin Strained-Si/SiGe Dual-Quantum Well

    Page(s): 603 - 605
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    This letter reports on the low-frequency flicker-noise characteristics in fresh and electrically stressed pMOSFETs with thin strained-Si (~4 nm)/Si0.6Ge0.4 (~4 nm) dual-quantum-well (DQW) channel architectures. Normalized power spectral density (NPSD) of Id fluctuations (SID/Id 2) in fresh DQW devices exhibits significant improvement (by >102times) due to buried channel operation at low Vg. At high Vg, the NPSD enhancement reduces as carriers populate in the parasitic surface channel. Upon electrical stress, noise behavior in DQW devices was found to evolve from being carrier number-fluctuation dominated to mobility- fluctuation dominated. This was accompanied by the observation of a "less-distinct" buried-channel operation, indicating a potential stability issue of the Si/SiGe structure. View full abstract»

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  • Effect of SiNx Gate Dielectric Deposition Power and Temperature on a-Si:H TFT Stability

    Page(s): 606 - 608
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    The stability of thin-film transistors (TFTs) of hydrogenated amorphous-silicon (a-Si:H) against gate-bias stress is improved by raising the deposition power and temperature of the silicon nitride gate dielectric. We studied the effects of power density between 22 and 110 mW/cm2 and temperature between 150degC and 300degC . The time needed to shift the threshold voltage by 2 V varies by a factor of 12 between low power and low temperature, and high power and high temperature. These results highlight the importance of fabricating a-Si:H TFTs on flexible plastic with the SiNx gate dielectric deposited at the highest possible power and temperature. View full abstract»

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  • Strained n-Channel Transistors With Silicon Source and Drain Regions and Embedded Silicon/Germanium as Strain-Transfer Structure

    Page(s): 609 - 612
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    We report the demonstration of 55 nm gate length strained n-channel field-effect transistors (n-FETs) having an embedded Si1-xGex structure that is beneath the Si channel region and which acts as a strain-transfer structure (STS). The Si1-xGex STS has lattice interactions with both the silicon source and drain regions and with the overlying Si channel region. This effectively results in a transfer of lateral tensile strain to the Si channel region for electron mobility enhancement. The mechanism of strain transfer is explained. Significant drive current Ion enhancement of 18% at a fixed off-state leakage Ioff of 100 nA/mum is achieved, which is attributed to the strain-induced mobility enhancement. Furthermore, continuous downsizing of transistors leads to higher Ion enhancement in the strained n-FETs, which is consistent with the increasing transconductance Gm improvement when the gate length is reduced. View full abstract»

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IEEE Electron Device Letters publishes original and significant contributions relating to the theory, modeling, design, performance and reliability of electron devices.

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