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IEEE Design & Test of Computers

Issue 2 • Date March-April 2007

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Displaying Results 1 - 25 of 29
  • [Front cover]

    Publication Year: 2007, Page(s): c1
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  • IEEE Computer Society Membership Information

    Publication Year: 2007, Page(s): c2
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  • Call for Papers: Special Issue on Design and Test of RFIC Chips

    Publication Year: 2007, Page(s): 105
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  • Table of contents

    Publication Year: 2007, Page(s):106 - 107
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  • Cocktail approach to functional verification

    Publication Year: 2007, Page(s): 108
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  • [Masthead]

    Publication Year: 2007, Page(s): 109
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  • Guest Editors' Introduction: Attacking Functional Verification through Hybrid Techniques

    Publication Year: 2007, Page(s):110 - 111
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  • A Survey of Hybrid Techniques for Functional Verification

    Publication Year: 2007, Page(s):112 - 122
    Cited by:  Papers (9)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (455 KB) | HTML iconHTML

    This article surveys recent advances in hybrid approaches for functional verification. These approaches combine multiple verification techniques so that they complement one another, resulting in superior verification effectiveness. View full abstract»

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  • Call for Papers

    Publication Year: 2007, Page(s): 123
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  • Hybrid Verification of Protocol Bridges

    Publication Year: 2007, Page(s):124 - 131
    Cited by:  Papers (1)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (791 KB) | HTML iconHTML

    It's usually necessary to apply formal verification on very small modules or else be content with bounded proofs on realistically large modules. But there is no denying that despite its capacity problems, formal verification has its strengths and utility and is a complementary technique to simulation. Used judiciously, simulation and formal techniques can complement each other's strengths, thereby... View full abstract»

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  • Combining Theorem Proving with Model Checking through Predicate Abstraction

    Publication Year: 2007, Page(s):132 - 139
    Cited by:  Papers (3)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (575 KB) | HTML iconHTML

    Using theorem-based approaches to prove the invariants of infinite-state reactive systems often demands significant manual involvement. This article presents a new approach in which model checking complements theorem proving, reducing the manual effort involved by transferring user attention from defining inductive invariants to proving rewrite rules. The authors use this approach with ACL2 to ver... View full abstract»

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  • Hybrid, Incremental Assertion-Based Verification for TLM Design Flows

    Publication Year: 2007, Page(s):140 - 152
    Cited by:  Papers (10)  |  Patents (2)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (962 KB) | HTML iconHTML

    Transaction-level modeling is an emerging design practice for overcoming increasing design complexity. This article proposes a methodology for verifying the correctness of RTL refinement from transaction-level modeling. The authors demonstrate the effectiveness of this methodology, guided by an assertion coverage metric on the modules of an industry design. View full abstract»

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  • Advertiser/Product Index

    Publication Year: 2007, Page(s): 153
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  • Hybrid Approach to Faster Functional Verification with Full Visibility

    Publication Year: 2007, Page(s):154 - 162
    Cited by:  Papers (6)  |  Patents (8)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (516 KB) | HTML iconHTML

    For functional verification, software simulation provides full controllability and observability, whereas hardware emulation offers speed. This article describes a new platform that leverages the advantages of both. This platform implements an efficient scheme to record the internal behavior of an FPGA emulator and replay the relevant segment of a simulation in a software environment for debugging... View full abstract»

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  • IEEE Computer Society Information

    Publication Year: 2007, Page(s): 163
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  • Economic Aspects of Memory Built-in Self-Repair

    Publication Year: 2007, Page(s):164 - 172
    Cited by:  Papers (15)  |  Patents (2)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (1093 KB) | HTML iconHTML

    With the advent of deep-submicron technology and SoC design methodology, it's possible to integrate heterogeneous cores from different sources in a single chip containing millions of gates. The yield of such a large chip is usually too low to be profitable. Therefore, yield enhancement is an important issue in SoC product development. Memory cores usually occupy a large proportion of the area of a... View full abstract»

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  • CiSE subscription information

    Publication Year: 2007, Page(s): 173
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  • Roundtable: Envisioning the Future for Multiprocessor SoC

    Publication Year: 2007, Page(s):174 - 183
    Cited by:  Papers (2)
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  • FSA SiP Market and Patent Analysis Report

    Publication Year: 2007, Page(s):184 - 192
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  • On the cusp of a validation wall

    Publication Year: 2007, Page(s):193 - 196
    Cited by:  Papers (30)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (884 KB) | HTML iconHTML

    Traditionally, universities teach how to make or build things but not so much how to "break" things or find, patch, or prevent breaks. However, much of industry validation hinges on the latter skills. Validation is something that does not get noticed when done well, but everyone notices when something goes wrong - such as the infamous Pentium floating-point division bug. Major semiconductor compan... View full abstract»

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  • Test Technology TC Newsletter

    Publication Year: 2007, Page(s): 197
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  • A textbook with two target audiences [review of VLSI Test Principles and Architecture by Laung-Terng Wang et al.; 2006]

    Publication Year: 2007, Page(s):198 - 199
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  • CEDA Currents

    Publication Year: 2007, Page(s):200 - 201
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  • Conference Reports

    Publication Year: 2007, Page(s):202 - 203
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  • Panel Summaries

    Publication Year: 2007, Page(s):204 - 206
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (96 KB) | HTML iconHTML

    1. IEEE International Workshop on Design For Manufacturing & Yield, Gary Smith (Gary Smith EDA)--On 26 October, the first Workshop on Design for Manufacturing & Yield (DFM&Y) was held in conjunction with the International Test Conference. In addition to regular and invited papers, the workshop included a very interesting panel session. This panel explored DFM, DFY, and RET, both in terms of techno... View full abstract»

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Aims & Scope

This Periodical ceased production in 2012. The current retitled publication is IEEE Design & Test.

Full Aims & Scope

Meet Our Editors

Editor-in-Chief
Krishnendu Chakrabarty