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Solid-State Circuits, IEEE Journal of

Issue 6 • Date June 2007

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Displaying Results 1 - 25 of 32
  • Table of contents

    Publication Year: 2007 , Page(s): C1 - C4
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  • IEEE Journal of Solid-State Circuits publication information

    Publication Year: 2007 , Page(s): C2
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  • Table of contents

    Publication Year: 2007 , Page(s): 1193 - 1194
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  • New Associate Editor

    Publication Year: 2007 , Page(s): 1195
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  • An Ultra Low Energy 12-bit Rate-Resolution Scalable SAR ADC for Wireless Sensor Nodes

    Publication Year: 2007 , Page(s): 1196 - 1205
    Cited by:  Papers (88)  |  Patents (5)
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (1587 KB) |  | HTML iconHTML  

    A resolution-rate scalable ADC for micro-sensor networks is described. Based on the successive approximation register (SAR) architecture, this ADC has two resolution modes: 12 bit and 8 bit, and its sampling rate is scalable, at a constant figure-of-merit, from 0-100 kS/s and 0-200 kS/s, respectively. At the highest performance point (i.e., 12 bit, 100 kS/s), the entire ADC (including digital, analog, and reference power) consumes 25 muW from a 1-V supply. The ADC's CMRR is enhanced by common-mode independent sampling and passive auto-zero reference generation. The efficiency of the comparator is improved by an analog offset calibrating latch, and the preamplifier settling time is relaxed by self-timing the bit-decisions. Prototyped in a 0.18-mum, 5M2P CMOS process, the ADC, at 12 bit, 100 kS/s, achieves a Nyquist SNDR of 65 dB (10.55 ENOB) and an SFDR of 71 dB. Its INL and DNL are 0.68 LSB and 0.66 LSB, respectively View full abstract»

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  • A Power-Efficient Two-Channel Time-Interleaved ΣΔ Modulator for Broadband Applications

    Publication Year: 2007 , Page(s): 1206 - 1215
    Cited by:  Papers (10)
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (1078 KB) |  | HTML iconHTML  

    A two-channel time-interleaved second-order sigma-delta modulator for broadband applications including asymmetrical digital subscriber line (ADSL) is presented. The proposed two-channel SigmaDelta modulator uses a single integrator channel which does not require additional active elements for the quantizer input generation, since the integrator outputs are directly used as the input of the quantizers. As a result, the entire modulator can be implemented using only two op-amps, which is beneficial for both power consumption and area. Furthermore, this architecture is robust to channel mismatch effects and can operate with a simple clocking scheme. The SigmaDelta modulator achieves a dynamic range of 85 dB over a 1.1-MHz signal bandwidth with an effective clock frequency of 132 MHz. The circuit is implemented in 0.18-mum CMOS technology using metal-insulator-metal capacitors. The total power consumption of the SigmaDelta modulator is 5.4mW from a 1.8-V supply and occupies an active area of 1.1 mm2 View full abstract»

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  • An SC Voltage Doubler with Pseudo-Continuous Output Regulation Using a Three-Stage Switchable Opamp

    Publication Year: 2007 , Page(s): 1216 - 1229
    Cited by:  Papers (18)  |  Patents (1)
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (1562 KB) |  | HTML iconHTML  

    This paper presents a switched-capacitor voltage doubler using pseudo-continuous control (PCC). The proposed PCC does not require extra power transistor to continuously regulate the output of the doubler, thereby saving chip area. The PCC also allows the doubler to operate at lower switching frequencies without sacrificing transient response. The light-load efficiency of the regulated doubler can thus be enhanced by reducing the switching power loss. In addition, a three-stage switchable opamp with time-multiplexed enhanced active-feedback frequency compensation is developed to implement the controller. The proposed implementation enhances the speed of the loop response and then improves the load transient response of the regulated doubler. The SC voltage doubler with the proposed PCC controller has been fabricated in a 0.6-mum CMOS process. The regulated doubler achieves >87% power efficiency even for the load current of 5 mA. By operating the doubler at switching frequency of 200 kHz and using a output capacitor of 2.2 muF, a maximum output ripple of 20mV is maintained for the load current changing from 50 mA to 150 mA. The output transient recovery time of the regulated doubler is ~25 mus with load-current step changes of 100 mA/1 mus View full abstract»

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  • A Low-Power 114-GHz Push–Push CMOS VCO Using LC Source Degeneration

    Publication Year: 2007 , Page(s): 1230 - 1239
    Cited by:  Papers (13)
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (1032 KB) |  | HTML iconHTML  

    An LC source-degeneration negative-resistance cell of an LC VCO is investigated, which is capable of operating at millimeter-wave (MMW) range with low dc power consumption. Several negative-resistance cells in LC oscillators are also compared. The LC source-degenerated topology is demonstrated through a 114-GHz push-push fully integrated LC VCO implemented in TSMC 0.13-mum CMOS process. With core power consumption of 8.4 mW, the tuning range at the fundamental port is 56.4-57.6 GHz and at the push-push port is 112.8-115.2 GHz. The measured phase noise at the fundamental port is -13.6 dBc/Hz at 10-MHz offset. This VCO is believed to have the best figure of merit among MMW VCOs using bulk CMOS processes. View full abstract»

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  • A 21-GHz 8-Modulus Prescaler and a 20-GHz Phase-Locked Loop Fabricated in 130-nm CMOS

    Publication Year: 2007 , Page(s): 1240 - 1249
    Cited by:  Papers (26)
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (1769 KB) |  | HTML iconHTML  

    A 1.5-V 256-263 8-modulus prescaler and a 1.5-V integer-N phase-locked loop (PLL) with eight different output frequencies have been implemented in a 0.13-mum foundry CMOS process. The synchronous divide-by-4/5 circuit uses current mode logic (CML) D-flip-flops with resistive loads to achieve 21-GHz maximum operating frequency at input power of 0 dBm. The divider is used to implement an 8-modulus prescaler consuming 6-mA current and 9-mW power. This extremely low power consumption is achieved by radically decreasing the sizes of transistors in the divider. Utilizing the prescaler, a charge-pump integer-N PLL has been demonstrated with 20-GHz output frequency. The in-band phase noise of the PLL at 60-kHz offset and out-of-band phase noise at 10-MHz offset are ~-80 dBc/Hz and -116.1 dBc/Hz, respectively. The locking range is from 20.05 to 21 GHz. The PLL consumes 15-mA current and 22.5-mW power from a 1.5-V power supply. View full abstract»

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  • A 1.5 V 3.1 GHz–8 GHz CMOS Synthesizer for 9-Band MB-OFDM UWB Transceivers

    Publication Year: 2007 , Page(s): 1250 - 1260
    Cited by:  Papers (10)
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (2045 KB) |  | HTML iconHTML  

    This paper presents the design of a CMOS synthesizer for dual-conversion zero-IF2 Multi-Band OFDM (MB-OFDM) transceivers covering the first 9 frequency bands from 3.1GHz to 8.0GHz, each with a bandwidth of 528 MHz. A wideband single-sideband mixer with wideband inductive network loading is proposed. Moreover, a modified transformer-coupled quadrature VCO and interconnection-loading-insensitive layout technique are employed. Fabricated in TSMC 0.18-mum CMOS process and operated at 1.5V, the synthesizer measures phase noise of -127.4dBc/Hz at 10MHz offset, integrated phase noise of 4.43deg, sideband suppression of better than -22 dBc, and a switching time of less than 1ns while consuming 59 mA View full abstract»

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  • A 1.2-V 37–38.5-GHz Eight-Phase Clock Generator in 0.13- μm CMOS Technology

    Publication Year: 2007 , Page(s): 1261 - 1270
    Cited by:  Papers (18)  |  Patents (2)
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (3513 KB) |  | HTML iconHTML  

    A 37-38.5-GHz clock generator is presented in this paper. An eight-phase LC voltage-controlled oscillator (VCO) is presented to generate the multiphase outputs. The high-pass characteristic CL ladder topology sustains the high-frequency signals. The split-load divider is presented to extend the input frequency range. The proposed PD improves the static phase error and enhances the gain. To verify the function of each block and modify the operation frequency, two additional testing components-an eight-phase VCO and a split-load frequency divider-are fabricated using 0.13-mum CMOS technology. The measured quadrature-phase outputs of VCO and input sensitivity of the divider are presented. This clock generator has been fabricated with 0.13-mum CMOS technology. The measured rms clock jitter is 0.24 ps at 38 GHz while consuming 51.6 mW without buffers from a 1.2-V supply. The measured phase noise is -97.55 dBc/Hz at 1-MHz offset frequency View full abstract»

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  • A Monolithic High-Efficiency 2.4-GHz 20-dBm SiGe BiCMOS Envelope-Tracking OFDM Power Amplifier

    Publication Year: 2007 , Page(s): 1271 - 1281
    Cited by:  Papers (102)  |  Patents (5)
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (1420 KB) |  | HTML iconHTML  

    A monolithic SiGe BiCMOS envelope-tracking power amplifier (PA) is demonstrated for 802.11g OFDM applications at 2.4 GHz. The 4-mm2 die includes a high-efficiency high-precision envelope amplifier and a two-stage SiGe HBT PA for RF amplification. Off-chip digital predistortion is employed to improve EVM performance. The two-stage amplifier exhibits 12-dB gain, <5% EVM, 20-dBm OFDM output power, and an overall efficiency (including the envelope amplifier) of 28%. View full abstract»

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  • A CDMA InGaP/GaAs-HBT MMIC Power Amplifier Module Operating With a Low Reference Voltage of 2.4 V

    Publication Year: 2007 , Page(s): 1282 - 1290
    Cited by:  Papers (8)  |  Patents (1)
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (1284 KB) |  | HTML iconHTML  

    This paper describes circuit design and measurement results of our newly developed InGaP/GaAs-HBT MMIC power amplifier (PA) module which can operate with 2.4-V low reference and low supply voltages of its on-chip bias circuits. To achieve the low-reference voltage operation, the following two new circuit design techniques are incorporated into the power amplifier: 1) AC-coupled, divided power stage configuration with two different kinds of bias feeding (voltage and current drive and only current drive) and 2) successful implementation of a diode linearizer built in the power stage. Theses two techniques allow the PA to offer smooth output transfer characteristics over a wide temperature range. Measurement results done under the conditions of 900 MHz, a 3.5-V collector voltage for power stage, and 2.4-V reference and collector voltages for the bias circuits show that the PA module meets J-/W-CDMA power and distortion requirements sufficiently over a wide temperature range from -10degC to 90degC while keeping a low quiescent current of less than 65 mA. For J-CDMA modulation, the module can deliver a 27.5-dBm output power (Pout), a 40% PAE, and a -50-dBc ACPR, while a 28-dBm Pout, a 42% PAE, and a -42-dBc ACLR are achieved for W-CDMA modulation. View full abstract»

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  • A Receiver Architecture for Dual-Antenna Systems

    Publication Year: 2007 , Page(s): 1291 - 1299
    Cited by:  Papers (7)  |  Patents (2)
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (1193 KB) |  | HTML iconHTML  

    The signals received by two antennas can be processed by a single time-shared receiver but only in the absence of interferers and channel-select filters. A low-IF receiver architecture is introduced that translates two antenna signals to positive and negative frequencies in the complex domain, reducing the number of baseband A/D converters by a factor of two. A dual-receiver prototype designed and fabricated in 0.18-mum CMOS technology provides a sensitivity of -72 dBm with an EVM of -25 dB for 64 QAM signals while drawing 60.2 mW from a 1.8-V supply. View full abstract»

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  • A UWB-IR Transmitter With Digitally Controlled Pulse Generator

    Publication Year: 2007 , Page(s): 1300 - 1309
    Cited by:  Papers (53)  |  Patents (5)
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (1966 KB) |  | HTML iconHTML  

    A novel transmitter for ultra-wideband (UWB) impulse radio has been developed. The proposed architecture enables low-power operation, simple design, and accurate pulse-shape generation. The phase and amplitude of the pulse are controlled separately and digitally to generate a desired pulse shape. This digital control method also contributes to the low-power transmission and eliminates the need for a filter. The transmitter is fabricated using a 0.18-mum CMOS process. The core chip size is only 0.40 mm2. From experimental measurements, it was found that the generated signal satisfied the FCC spectrum mask, and the average power dissipation was only 29.7 mW at A 2.2-V supply voltage. Therefore, the developed UWB transmitter generates accurate pulses with low power consumption and simple design architecture View full abstract»

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  • A 750 mV Fully Integrated Direct Conversion Receiver Front-End for GSM in 90-nm CMOS

    Publication Year: 2007 , Page(s): 1310 - 1317
    Cited by:  Papers (16)  |  Patents (4)
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (1418 KB) |  | HTML iconHTML  

    The design of RF integrated circuits, at the low voltage allowed by sub-scaled technologies, is particularly challenging in cellular phone applications where the received signal is surrounded by huge interferers, determining an extremely high dynamic range requirement. In-depth investigations of 1/f noise sources and second-order intermodulation distortion mechanisms in direct downconversion mixers have been carried out in the recent past. This paper proposes a fully integrated receiver front-end, including LNA and quadrature mixer, supplied at 750 mV, able to meet GSM specifications. In particular, the direct downconverter employs a feedback loop to minimize second-order common mode intermodulation distortion, generated by a pseudo-differential transconductor, adopted for minimum voltage drop. For maximum dynamic range, the commutating pair is set with an LC filter. Prototypes, realized in a 90-nm RF CMOS process, show the following performances: 51 dBm IIP2, minimum over 25 samples, 1 dB desensitization point due to 3-MHz blocker at -18 dBm, 3.5 dB noise figure (NF), integrated between 1 kHz-100 kHz, 15 kHz 1/f noise corner. The front-end IIP2 has also been characterized with the mixer feedback loop switched off, resulting in an average reduction of 18 dB. View full abstract»

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  • A 0.25-μm CMOS 1.9-GHz PHS RF Transceiver With a 150-kHz Low-IF Architecture

    Publication Year: 2007 , Page(s): 1318 - 1327
    Cited by:  Papers (2)
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (2704 KB) |  | HTML iconHTML  

    We present a 1.9-GHz Personal Handy-phone System (PHS) transceiver, fully integrated and fabricated in 0.25-mum CMOS technology. The receiver is based on a 150-kHz low-IF architecture and meets the fast channel switching and DC-offset cancellation requirements of PHS. It includes a low-noise amplifier (LNA), a downconversion mixer, a complex filter, and a programmable gain amplifier. A fractional-N frequency synthesizer achieves seamless handover with a 25 mus channel switching time and a phase noise of -121 dBc/Hz at a 600-kHz offset frequency, with compliant ACS performance. The receiver provides -105 dBm sensitivity and 55 dBc ACS at a 600-kHz frequency offset. The transmitter is based on the direct modulation architecture and consists of an upconversion mixer and a pre-driver stage. The gain of the pre-driver is digitally controllable to suit any type of commercial power amplifier. The transmitter shows a 3% EVM and a 65 dBc ACPR at a 600-kHz offset frequency. The whole transceiver occupies 15.2 mm2 and dissipates 70 mA in RX and 44 mA in TX, with a 2.8-V supply View full abstract»

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  • A CDMA Dual-Band Zero-IF Receiver With Integrated LNAs and VCOs in an Advanced SiGe BiCMOS Process

    Publication Year: 2007 , Page(s): 1328 - 1338
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (2587 KB) |  | HTML iconHTML  

    This paper describes one of the first dual PCS- and CEL-band CDMA receivers that includes LNAs and VCOs on a single die. The PCS-band LNA achieves a noise figure (NF) of 1.5dB and IP3 of +7.5 dBm at 16-dB gain. The PCS demodulating mixer achieves an NF of 5 dB, IP3 of +5 dBm and uncalibrated IP2 of +60 dBm. The PCS VCO is capable of -134 dBc/Hz phase noise at 3.9 GHz and 1.25-MHz offset. A copper BiCMOS process was chosen for both performance and cost benefits, compared with lower geometry CMOS View full abstract»

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  • Generalized Linear Periodic Time-Varying Analysis for Noise Reduction in an Active Mixer

    Publication Year: 2007 , Page(s): 1339 - 1351
    Cited by:  Papers (3)
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (792 KB) |  | HTML iconHTML  

    A simple linear periodic time-varying circuit model is proposed to rigorously analyze the noise behavior in an active mixer. This analysis can be shown to be a generalization of existing LPTV mixer models, which assume that the mixer is a memoryless device and, as a result, is valid for low frequency only. Based on the proposed LPTV circuit model, explicit formulas for noise figure that accounts for the effect of the thermal noise folding and the flicker noise leakage are derived. Our analysis shows that the mixer operating at OFF overlap mode yields a better noise performance. The analysis is validated against simulations and measurements. View full abstract»

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  • A Complementary Switched MOSFET Architecture for the 1/f Noise Reduction in Linear Analog CMOS ICs

    Publication Year: 2007 , Page(s): 1352 - 1361
    Cited by:  Papers (6)  |  Patents (3)
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (1710 KB) |  | HTML iconHTML  

    We present a novel principle for 1/f noise reduction in linear analog CMOS ICs. The principle is experimentally demonstrated for a two-stage CMOS Miller operational amplifier in a standard 0.12-mum, 1.5-V digital CMOS technology. A threefold 1/f noise reduction (5 dB) is achieved at 10 Hz compared with a reference circuit. The impact of the principle on the circuit performance is investigated View full abstract»

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  • Random Telegraph Signal in Flash Memory: Its Impact on Scaling of Multilevel Flash Memory Beyond the 90-nm Node

    Publication Year: 2007 , Page(s): 1362 - 1369
    Cited by:  Papers (24)  |  Patents (1)
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (2118 KB) |  | HTML iconHTML  

    Threshold-voltage (Vth) fluctuation due to random telegraph signal (RTS) in flash memory was observed for the first time. A large amount of data of Vth fluctuation was acquired by using a 90-nm-node memory array, and it was confirmed that a few memory cells have large RTS fluctuation exceeding 0.2 V. It was found that program-and-erase cycles increase Vth amplitude in a flash memory. It was also found by simulation and measurement that tail-bits are generated due to RTS in multilevel flash operation. The amount of Vth broadening due to the tail-bits was estimated to become larger as the scaling of memory cells advances and reaches more than 0.3 V in the 45-nm node. These results thus demonstrate that RTS will become a prominent issue in designing multilevel flash memory in the 45-nm node and beyond. View full abstract»

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  • Design of a Process Variation Tolerant Self-Repairing SRAM for Yield Enhancement in Nanoscaled CMOS

    Publication Year: 2007 , Page(s): 1370 - 1382
    Cited by:  Papers (28)
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (3189 KB) |  | HTML iconHTML  

    In nanoscaled technologies, increased inter-die and intra-die variations in process parameters can result in large number of parametric failures in an SRAM array, thereby, degrading yield. In this paper, we propose a self-repairing SRAM to reduce parametric failures in memory. In the proposed technique, on-chip monitoring of leakage current and/or delay of a ring oscillator is used to determine the inter-die process corner of an SRAM die. Depending on the inter-die Vt shift, the self-repair system selects the proper body bias to reduce parametric failures. Simulations using predictive 70-nm device show that the proposed self-repairing SRAM improves design yield by 5%-40%. A test-chip is designed and fabricated in IBM 0.13-mum CMOS technology to successfully demonstrate the operation of the self-repair system. View full abstract»

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  • An Embeddable Multilevel-Cell Solid Electrolyte Memory Array

    Publication Year: 2007 , Page(s): 1383 - 1391
    Cited by:  Papers (3)  |  Patents (1)
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (1759 KB) |  | HTML iconHTML  

    Nonvolatile memory cells based on solid electrolytes have many desirable attributes, including low-voltage and low-current operation and a simple process that allows them to be integrated with conventional CMOS processes with minimal additional masking layers. In this paper, we present a 2-kb memory block/testbed (1024 elements) using solid electrolyte cells. The compact memory design addresses many of the unusual operational issues associated with the solid electrolyte elements and allows for two digital bits to be stored and read from each cell with minimal circuitry. The design was fabricated in 0.18-mum CMOS technology and the simulation and physical data are presented. Multilevel-cell (MLC) operation was demonstrated for a 10-muA reference current with a 437-ns cycle time and sub-40-ns access times View full abstract»

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  • The Effect of the System Specification on the Optimal Selection of Clocked Storage Elements

    Publication Year: 2007 , Page(s): 1392 - 1404
    Cited by:  Papers (15)
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (2611 KB) |  | HTML iconHTML  

    This paper represents a departure from the conventional methods of design and analysis of clocked storage elements that rely on minimizing a fixed energy-delay metric. Instead it establishes a systematic comparison in the energy-delay design space based on the parameters of the surrounding blocks. We define the composite energy-efficient characteristic over all storage element topologies and identify the most efficient storage element depending on its position on the composite characteristic relative to other topologies within a pipeline stage. Thus, we show that an optimal design could use a mixed variety of clocked storage elements (CSEs) depending on their placement in the pipeline and critical path. Since a well-designed system has hardware intensities balanced for a given cycle, a CSE choice will be made depending on the pipeline and path intensities. We show that a meaningful comparison can be carried out only by acknowledging that the optimal design and choice of the clocked storage elements depends heavily on the application, and by analyzing the energy and delay of the clocked storage elements in context of this application. The analysis in the energy-delay space allows us to understand some intuitive design choices in a quantitative way and to identify the optimal storage element topologies for an arbitrary system specification View full abstract»

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  • Surfing Pipelines: Theory and Implementation

    Publication Year: 2007 , Page(s): 1405 - 1414
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (814 KB) |  | HTML iconHTML  

    Surfing is a latchless pipelining technique where the propagation delays of gates and other logic functions are modulated to produce event attractors. Timing events are propagated along the pipeline and events in the data path are attracted to coincide with the timing events. These attractors reduce timing uncertainties and can reduce the delays of the pipeline. We demonstrate surfing by the design, fabrication, and test of a chip. The surfing ring in this chip supports two independent waves of computation separated only by the surfing effect-no latches or other storage elements are used. We operated the ring for over 48 h and 2 times 1015 surfing events and never observed an error. View full abstract»

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Aims & Scope

The IEEE Journal of Solid-State Circuits publishes papers each month in the broad area of solid-state circuits with particular emphasis on transistor-level design of integrated circuits.

Full Aims & Scope

Meet Our Editors

Editor-in-Chief
Michael Flynn
University of Michigan