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IEEE Design & Test of Computers

Issue 4 • Aug. 1988

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  • Analysis of testable PLA designs

    Publication Year: 1988, Page(s):14 - 28
    Cited by:  Papers (18)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (1116 KB)

    A framework is presented for evaluating methods of testing programmable logic arrays (PLAs), and the attributes of 25 test design methodologies are tabulated. PLA testing problems are first examined, and several test-generation algorithms are briefly described. Techniques for designing testable designs are examined, namely, special coding, parity checking, signature analysis, divide and conquer, a... View full abstract»

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  • Built-in test for RAMs

    Publication Year: 1988, Page(s):29 - 36
    Cited by:  Papers (14)  |  Patents (6)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (718 KB)

    A built-in test structure is described that is based on the ATS algorithmic test sequence, which provides the shortest possible test for stuck-at faults in a random-access memory (RAM). An initialization step has been added to ATS that allows the modified procedure to detect bit-rail faults. In the test mode, the memory address register is converted to a count-by-three circuit controlled by a four... View full abstract»

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  • Built-in self-test of a CMOS ALU

    Publication Year: 1988, Page(s):38 - 48
    Cited by:  Papers (5)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (886 KB)

    A technique is proposed for implementing BIST (built-in self-test) in a CMOS arithmetic and logic unit (ALU). The approach covers single stuck-open faults and all functional faults that do not induce memory effects. The specific fault set covered by the test includes: (1) all single stuck-open faults on n and p transistors anywhere in the ALU (F1 faults); and (2) all functional faults that affect ... View full abstract»

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This Periodical ceased production in 2012. The current retitled publication is IEEE Design & Test.

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